DS855 Datasheet, PDF (7/8 Pages) Xilinx, Inc – Has user-selectable number of Kintex-7 FPGA GTX transceivers

ChipScope IBERT for Kintex-7 GTX (v2.01.a)
Ordering Information
The IBERT core is provided under the Integrated Software Environment (ISE®) Design Suite End-User License
Agreement and can be generated using the Xilinx CORE Generator™ system 13.3 or higher. The CORE Generator
system is shipped with Xilinx ISE Design Suite development software.
Contact your local Xilinx sales representative for pricing and availability of additional Xilinx LogiCORE IP modules
and software. Information about additional Xilinx LogiCORE IP modules is available on the Xilinx IP Center.
List of Acronyms
Acronym
CPRI
DFE
DRP
FF
FPGA
IBERT
I/O
ILA
ISE
JTAG
LUT
MMCM
MHz
PCS
PLL
PMA
PRBS
RAM
RX
TX
XAUI
Spelled Out
Common Packet Radio Interface
Decision Feedback Equalizer
Dynamic Reconfiguration Port
Flip-Flop
Field Programmable Gate Array
Integrated Bit Error Ratio Tester
Input/Output
Integrated Logic Analyzer
Integrated Software Environment
Joint Test Action Group
Lookup Table
Mixed-Mode Clock Manager
Mega Hertz
Physical Coding Sublayer
Phase-Locked Loop
Physical Medium Attachment
Pseudorandom binary sequence
Random Access Memory
Receive
Transmit
eXtended Attachment Unit Interface
Revision History
The table shows the revision history for this document:
Date
06/22/2011
10/19/2011
Version
1.0
2.0
Description of Revisions
Initial Xilinx release
Added configuration information, new signals to Table 1, devices to Table 2.
Updated for the IDS 13.3. software.
DS855 October 19, 2011
www.xilinx.com
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Product Specification