DS855 Datasheet, PDF (5/8 Pages) Xilinx, Inc – Has user-selectable number of Kintex-7 FPGA GTX transceivers

ChipScope IBERT for Kintex-7 GTX (v2.01.a)
Receiver Output Clock
The receiver clock probe enable is provided if you want to pull out a recovered clock from any serial transceiver.
When enabled, a new panel appears just before the summary page where you can fill in the serial transceiver source
and probe pin standards.
GTX Transceiver Naming Style
There are two conventions for the GTX transceiver name based on the location in the serial transceiver tile in the
device. M and n in XmYn naming convention indicate the X and Y coordinates of the serial transceiver location. M
and n in serial transceiver m_n naming convention indicating serial transceiver number and quad associated.
System Clock
The IBERT core requires a free-running system clock to clock the communication and other logic included in the
core. This clock can be chosen at generation time to come from an FPGA pin, or be driven from the TXOUTCLK port
of one of the GTX transceivers in the core. In order for the core to operate properly, this system clock source must
remain operational and stable when the FPGA is configured with the IBERT core design. If the system clock is
running faster than 150 MHz, it is divided down internally using an Mixed-Mode Clock Manager (MMCM) to
satisfy timing constraints.
Line Rate Support
IBERT supports a maximum of three different line rates in a single design. For each of these line rates, select a
custom value based on your requirements. You can also choose from pre-provided industry standard protocols
such Common Packet Radio Interface (CPRI™), gigabit Ethernet, eXtended Attachment Unit Interface (XAUI). For
each line rate, you should specify the number of serial transceivers that will be programmed with these settings.
Because usage of QPLL is recommended for line rates above 6.5 Gb/s, you are given a choice to select QPLL/CPLL
for each line rate falling in the range 0.6 Gb/s to 6.5 Gb/s.
Serial Transceiver Location
Based on the total number of serial transceivers selected in the previous panel, you should provide the specific
location of each serial transceiver that you intend to use. The region shown in the panel indicates the location of
serial transceivers in the tile. This demarcation of region is based on the physical placement of serial transceivers
with respect to median of BUFGs available for each device.
Reference Clock
For all the serial transceivers selected, the reference clock source should be provided. The drop-down list provides
you with possible sources based on local clocks in the same quad and shared clocks from north/south quads.
Generating the Core
After entering the IBERT core parameters, click Generate to create the IBERT core files. After the IBERT core has
been generated, a list of files that are generated will appear in a separate window called "Readme <corename>".
DS855 October 19, 2011
www.xilinx.com
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Product Specification