DS855 Datasheet, PDF (1/8 Pages) Xilinx, Inc – Has user-selectable number of Kintex-7 FPGA GTX transceivers

DS855 October 19, 2011
ChipScope Pro Integrated
Bit Error Ratio Test (IBERT)
for Kintex-7 FPGA GTX (v2.01.a)
Product Specification
Introduction
The ChipScope™ Pro IBERT core for Kintex™-7 FPGA
GTX transceivers is customizable and designed for
evaluating and monitoring Kintex-7 FPGA GTX
transceivers. This core includes pattern generators and
checkers that are implemented in FPGA logic, and
access to ports and the dynamic reconfiguration port
attributes of the GTX transceivers. Communication
logic is also included to allow the design to be run-time
accessible through JTAG. This core can be used as a self-
contained or an open design, based on customer
configuration, and as described in this document.
Features
• Provides a communication path between the
ChipScope Pro Analyzer software and the IBERT
core.
• Has user-selectable number of Kintex-7 FPGA GTX
transceivers.
• Each transceiver can be customized for the desired
line rate, reference clock rate, reference clock
source, and datapath width.
• Requires a system clock that can be sourced from a
pin or one of the enabled GTX transceivers.
LogiCORE IP Facts Table
Core Specifics
Supported
Device
Family ⁽¹⁾
Supported
User Interfaces
Resources ⁽²⁾
Kintex-7
N/A
Frequency
Configuration LUTs FFs
DSP Block
Slices ^RAMs
Max. Freq⁽³⁾
Config1
Config2
Config3
2401 4120
0
0
8359 14533 0
0
23516 41022 0
0
Provided with Core
306.551 MHz
295.859 MHz
246.233 MHz
Documentation
Design Files
Example
Design
Test Bench
Constraints
File
Simulation
Model
Product Specification
User Guide
Netlist
Verilog/VHDL
Not Provided
Xilinx Constraints and Synthesis Constraints
Tested Design Tools
Not Provided
Design Entry
Tools
Simulation
Synthesis
Tools
Xilinx CORE Generator™ tool
Not Provided
Not Provided
Support
Provided by Xilinx @ www.xilinx.com/support
1. Including the variants of this FPGA device.
2. Resources listed here are for Kintex-7 devices. For more complete
device performance numbers, see Table 2.
3. Performance numbers listed are for Kintex-7 FPGAs. For more
complete performance data, see Performance and Resource
Utilization.
© Copyright 2011 Xilinx, Inc. Xilinx, the Xilinx logo, Artix, ISE, Kintex, Spartan, Virtex, Zynq, and other designated brands included herein are trademarks of Xilinx in
the United States and other countries. CPRI is a trademark of Siemens AG. All other trademarks are the property of their respective owners.
DS855 October 19, 2011
www.xilinx.com
1
Product Specification