DS855 Datasheet, PDF (4/8 Pages) Xilinx, Inc – Has user-selectable number of Kintex-7 FPGA GTX transceivers

ChipScope IBERT for Kintex-7 GTX (v2.01.a)
Pattern Generation and Checking
Each GTX transceiver enabled in the IBERT design has both a pattern generator and a pattern checker. The pattern
generator sends data out through the transmitter. The pattern checker takes the data coming in through the receiver
and checks it against an internally generated pattern. IBERT offers PRBS 7-bit, PRBS 15-bit, PRBS 23-bit, PRBS31-bit,
Clk 2x (101010...) and Clk 10x(11111111110000000000...) patterns.
These patterns are optimized for the logic width chosen, and are selectable at run time. The TX pattern and RX
pattern are individually selectable.
The Analyzer software displays a ‘link’ signal until there are five consecutive cycles with errors. Using the pattern
checker logic, the incoming data is compared against a pattern that is internally generated. When the checker
receives five consecutive cycles of data with errors, the Analyzer software disables the link signal. Internal counters
accumulate the number of words and error received.
DRP and Port Access
IBERT also provides flexibility for users to change GTX transceiver ports and attributes. DRP interface logic is
included in the IBERT core to allow the run-time software to monitor and change any attribute in any of the GTX
transceivers and the corresponding CPLL/QPLL. When applicable, readable and writable registers are also
included that are connected to the various ports of the GTX transceiver. All are accessible at run time using the
ChipScope Analyzer tool.
Xilinx CORE Generator Tool
The Xilinx CORE Generator tool allows you to define and generate a customized IBERT core to use to validate the
transceivers of the device. You can customize the number of serial transceivers, line rate and reference clock, and
PLL selection for each serial transceiver.
Entering the Component Name
The Component Name field, stored as component_name in the generated XCO parameter file, can consist of any
combination of alpha-numeric characters in addition to the underscore symbol. However, the underscore symbol
cannot be the first character in the component name.
Generating an Example Design
The IBERT CORE Generator tool normally generates example design along with standard Xilinx CORE Generator
output files, such as a netlist and instantiation template files. Example design and Implement scripts are generated
under the folder with the component name.
Generate Bitstream
The Generate Bitstream by default is enabled and when it is generated, it runs through the entire implementation
flow, including bitstream generation. When Generate Bitstream is disabled and generated, the design will run
through synthesis. You can edit the example design and embed the custom design along with the IBERT instance.
The implement script provided with the generated files allows you to run the example design until bitstream
generation.
DS855 October 19, 2011
www.xilinx.com
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Product Specification