DS855 Datasheet, PDF (6/8 Pages) Xilinx, Inc – Has user-selectable number of Kintex-7 FPGA GTX transceivers

ChipScope IBERT for Kintex-7 GTX (v2.01.a)
IBERT Interface Ports
The I/O signals of the IBERT core consist only of the GTX transceiver reference clocks, the GTX transceiver transmit
and receive pins, and a system clock (optional).
Table 1: Interface Ports
Port Name
Direction
Description
IBERT_SYSCLOCK_I
CONTROL[35:0]
XiYj_TX_P_OPAD-1:0] ⁽¹⁾
XiYj_TX_P_OPAD[n-1:0]⁽¹⁾
XiYj_RX_N_IPAD[n-1:0]⁽¹⁾
XiYj_RX_P_IPAD[n-1:0]⁽¹⁾
MGTREFCLK_P[m-1:0]⁽²⁾
XiYj_RXOUTCLK_O⁽¹⁾
IN
IN/OUT
OUT
Clock that clocks all communication logic. This port is present only when an
external clock is selected in the generator.
Control bus connection to the ICON core.
Transmit differential pairs for each of the n GTX transceivers used.
IN
Receive differential pairs for each of the n GTX transceivers used.
IN
OUT
GTX transceiver reference clocks used.
Note: The number of MGTREFCLK ports can be equal to or less than the
number of transmit and receive ports because some GTX transceivers can share
clock inputs.
Quad based RX output clock.
1. The XiYj name refers to the GTX site location.
2. The Qk name refers to the GTX quad site location.
Performance and Resource Utilization
Table 2: Configuration Details
Configuration Name Device
IBERT Setup
Config1
XC7K325T-2FFG900
1 serial transceiver with line rate set to 10.3125 Gb/s
Config2
XC7K325T-2FFG900
4 serial transceivers with line rate set to 10.3125 Gb/s
Config3
XC7K325T-2FFG900
12 serial transceivers with line rate set to 10.3125 Gb/s
Verification
Xilinx has verified the IBERT core in a proprietary test environment, using an internally developed bus functional
model.
References
• More information on the ChipScope Pro software and cores is available in the Software and Cores User Guide,
located at www.xilinx.com/documentation.
• For more information about the Kintex-7 FPGA GTX transceiver, see the 7 Series FPGAs GTX Transceivers User
Guide, located at www.xilinx.com/documentation.
Support
Xilinx provides technical support for this LogiCORE™ IP product when used as described in the product
documentation. Xilinx cannot guarantee timing, functionality, or support of product if implemented in devices that
are not defined in the documentation, if customized beyond that allowed in the product documentation, or if
changes are made to any section of the design labeled DO NOT MODIFY.
DS855 October 19, 2011
www.xilinx.com
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Product Specification