DS855 Datasheet, PDF (2/8 Pages) Xilinx, Inc – Has user-selectable number of Kintex-7 FPGA GTX transceivers

ChipScope IBERT for Kintex-7 GTX (v2.01.a)
Applications
The IBERT core is designed to be used in any application that requires verification or evaluation of Kintex-7 FPGA
GTX transceivers.
Functional Description
The IBERT core provides a broad-based Physical Medium Attachment (PMA) evaluation and demonstration
platform for Kintex-7 FPGA GTX transceivers. Parameterizable to use different GTX transceivers and clocking
topologies, the IBERT core can also be customized to use different line rates, reference clock rates, and logic widths.
Data pattern generators and checkers are included for each GTX transceiver desired, giving a variety of different
Pseudo-random binary sequence (PRBS) and clock patterns to be sent over the channels. The configuration and
tuning of the GTX transceivers is accessible though logic that communicates to the DRP port of the GTX transceiver.
This allows changing attribute settings and registers that control the values on the ports. At run time, the ChipScope
Analyzer tool communicates to the IBERT core through JTAG, using the Xilinx cables and proprietary logic that is
part of the IBERT core.
GTX Transceiver Features
IBERT is designed for Physical Medium Attachment (PMA) evaluation and demonstration. All the major PMA
features of the GTX transceiver are supported and controllable in IBERT, including:
• TX pre-emphasis and post-emphasis
• TX differential swing
• RX equalization
• Decision Feedback Equalizer (DFE)
• Phase-Locked Loop (PLL) Divider settings
Some of the Physical Coding Sublayer (PCS) features offered by the transceiver are outside the scope of IBERT,
including
• Clock Correction
• Channel Bonding
• 8B/10B, 64B/66B, or 64B/67B encoding
• TX or RX Buffer Bypass
PLL Configuration
For each Serial Transceiver Channel, there is a ring Phase-Locked Loop (PLL) called Channel PLL (CPLL). The GTX
in the Kintex-7 FPGA has an additional shared PLL per quad, Quad PLL (QPLL). This QPLL is shared LC PLL to
support high speed, high performance and low power multi-lane applications.
Figure 1 shows a Quad in a Kintex-7 device. The GTXE2_CHANNEL component has the serial transceiver and
CPLL units and the GTXE2_COMMON has the QPLL unit.
DS855 October 19, 2011
www.xilinx.com
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Product Specification