DS622 Datasheet, PDF (7/8 Pages) Xilinx, Inc – Wrapper around the PLL_ADV primitive

Phase Locked Loop (PLL) Module (v2.00a)
Table 2: PLL Module Input and Output Signals
CLKFBIN
CLKIN1
RST
Input
Input
Input
Register Descriptions
Not Applicable.
Clock feedback input
Primary clock input
Asynchronous reset signal
Timing Diagrams
See the Virtex-5 User Guide for more information.
Design Implementation
Target Technology
This module is intended for use on Spartan-6 and Virtex-5 FXT devices (the PLL_ADV primitive is
available on all Virtex-5 devices).
Device Utilization and Performance Benchmarks
This module uses one PLL primitive and one BUFG primitive for each clock output that is used.
Reference Documents
1. UG190 Virtex-5 User Guide
2. Virtex-5 Libraries Guide for HDL Designs
Revision History
Date
4/27/07
4/10/08
11/17/08
6/24/09
Version
Revision
1.0
Initial Xilinx release.
1.1
The PLL Module wrapper does not perform any error checking to enforce the design
rules and restrictions described in the Virtex-5 User Guide.
1.2
Incorporated CR473092; corrected PDF properties; converted to current DS
template; updated trademark/registration symbol usage; updated links
1.3
Updated for EDK_L 11.2; created v2.00a.
DS622 June 24, 2009
www.xilinx.com
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Product Specification