DS622 Datasheet, PDF (6/8 Pages) Xilinx, Inc – Wrapper around the PLL_ADV primitive

Phase Locked Loop (PLL) Module (v2.00a)
Allowable Parameter Combinations
The C_CLKOUTn_DESKEW_ADJUST parameter must be set to NONE for clock outputs connected to
the CPMC440CLK and CPMINTERCONNECTCLK pins on the ppc440 primitive in Virtex-5 FXT.
Clock output signals connected to any other pins on the ppc440 primitive must have the
C_CLKOUTn_DESKEW_ADJUST parameter set to PPC. Clock output signals connected to soft logic
modules that connect to the ppc440 primitive must have the C_CLKOUTn_DESKEW_ADJUST
parameter set to PPC. For Virtex-5 FXT designs, the C_CLKFBOUT_BUF parameter must be set to true
when used in the recommended configuration shown in Figure 1. For Virtex-5 FXT designs, the
C_CLKOUTn_BUF parameters must be set to true for any clock output that is used. The PLL_ADV
primitive has additional restrictions on parameter combinations that are allowed for Virtex-5 FXT
designs. The restrictions are documented in the Virtex-5 User Guide and Virtex-5 Libraries Guide.
Note: The PLL Module wrapper does not perform any error checking to enforce the design rules and
restrictions described in the Virtex-5 User Guide.
PLL Module I/O Signals
The input and output signals of the PLL module are described in Table 2.
The table below contains an example of how to create cross-references from the table body to the table
notes.
Table 2: PLL Module Input and Output Signals
CLKFBDCM
CLKFBOUT
CLKOUT0
CLKOUT1
CLKOUT2
CLKOUT3
CLKOUT4
CLKOUT5
CLKOUTDCM0
CLKOUTDCM1
CLKOUTDCM2
CLKOUTDCM3
CLKOUTDCM4
CLKOUTDCM5
LOCKED
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Output
Same as PLL_ADV
primitive
Feedback clock signal to use when the PLL drives
a DCM or is driven by a DCM
Feedback clock output to be connected to
CLKFBIN
Clock output 0
Clock output 1
Clock output 2
Clock output 3
Clock output 4
Clock output 5
Local copy of CLKOUT0 that connects to the DCM
within the same tile
Local copy of CLKOUT1 that connects to the DCM
within the same tile
Local copy of CLKOUT2 that connects to the DCM
within the same tile
Local copy of CLKOUT3 that connects to the DCM
within the same tile
Local copy of CLKOUT4 that connects to the DCM
within the same tile
Local copy of CLKOUT5 that connects to the DCM
within the same tile
Synchronous output that goes high when the PLL
has achieved phase alignment and frequency
matching
6
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DS622 June 24, 2009
Product Specification