DS622 Datasheet, PDF (2/8 Pages) Xilinx, Inc – Wrapper around the PLL_ADV primitive

Phase Locked Loop (PLL) Module (v2.00a)
Functional Description
The PLL Module takes an input clock named CLKIN1, then generates several output clocks, each of
which can be configured to have a different frequency that is dependent on the input clock frequency.
The PLL Module encapsulates the PLL_ADV primitive as shown in Figure 1. The PLL_ADV primitive
is described in the Libraries Guide for the applicable family that is provided as part of the ISE tools
documentation.
The PLL Module provides optional buffers for the CLKIN1 input, and the CLKOUT*, and CLKFBOUT
outputs. CLKOUT* represents the six clock outputs CLKOUT0, CLKOUT1, CLKOUT2, CLKOUT3,
CLKOUT4, and CLKOUT5. The second clock input of the PLL_ADV primitive is not used, and the
clock input select input of the PLL_ADV primitive is connected to a constant to always select the
CLKIN1 signal. The dynamic reconfiguration inputs and outputs of the PLL_ADV primitive are
hidden or terminated within the PLL module, as is the control input for the PMCD mode. All other
inputs and outputs of the PLL_ADV primitive are inputs and outputs of the PLL module.
Figure Top x-ref 1
PLL_MODULE
CLKIN1
BUFG
BUFG
CLKOUT*
CLKFBIN
Other Inputs
PLL_ADV
PRIMITIVE
BUFG
Other Outputs
CLKFBOUT
Figure 1: PLL Module Implementation and Usage
DS622_01_111708
In the context of an embedded processor system, the recommended usage of the PLL module is to take
a single reference clock input, then configure the CLKOUT* signals to produce the different clock
frequencies and phases required, with the CLKOUT* and CLKFBOUT signals buffered and connected
as shown by the dashed lines in Figure 1.
The output clock frequencies are derived from the input clock frequency, and the values of the
following parameters: C_DIVCLK_DIVIDE, C_CLKFBOUT_MULT, C_CLKOUTn_DIVIDE.
Frequency of CLKOUTn = Frequency of CLKIN1 * (C_CLKFBOUT_MULT/C_DIVCLK_DIVIDE) /
C_CLKOUTn_DIVIDE
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DS622 June 24, 2009
Product Specification