DS622 Datasheet, PDF (5/8 Pages) Xilinx, Inc – Wrapper around the PLL_ADV primitive

Phase Locked Loop (PLL) Module (v2.00a)
Table 1: MPD Parameters for PLL Module (Cont’d)
Parameter Name
Description
Allowed
Values
C_CLKOUT4_
DUTY_CYCLE
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_CLKOUT4_PHASE
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_CLKOUT5_BUF
If C_CLKOUT5_BUF = true, a BUFG
is inserted between the CLKOUT5
pin of the PLL_ADV primitive and
CLKOUT5 output
true, false
C_CLKOUT5_DESKEW Clock delay attribute for CLKOUT5 NONE,
_ADJUST
output
PPC⁽¹⁾
C_CLKOUT5_DIVIDE
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_CLKOUT5_
DUTY_CYCLE
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_CLKOUT5_PHASE
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_COMPENSATION
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_DIVCLK_DIVIDE
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
IF C_EXT_RESET_HIGH = 0, the
C_EXT_RESET_HIGH RST signal is inverted before
0,1
connecting to the PLL_ADV
C_FAMILY
Target FPGA family
virtex5,
virtex5fx,
spartan6,
spartan6t
C_REF_JITTER
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_RESET_ON_LOSS_
OF_LOCK
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
C_RST_DEASSERT_
CLK
This parameter passes the value to
the equivalent attribute of the
PLL_ADV
Same as
PLL_ADV
Default Value Type
0.5
real
0.0
real
false
Boolean
NONE
1
string
integer
0.5
real
0.0
real
SYSTEM_
SYNCHRONOUS
string
1
integer
1
integer
NONE
string
0.1
real
false
Boolean
CLKIN1
string
Notes:
1. The C_CLKOUTn_DESKEW_ADJUST value “PPC” applies only to Virtex-5 FXT designs.
DS622 June 24, 2009
www.xilinx.com
5
Product Specification