DS622 Datasheet, PDF (1/8 Pages) Xilinx, Inc – Wrapper around the PLL_ADV primitive

DS622 June 24, 2009
Phase Locked Loop
(PLL) Module (v2.00a)
Product Specification
Introduction
The Phase Locked Loop primitive in Virtex-5 and
Spartan-6 parts is used to generate multiple clocks with
defined phase and frequency relationships to a given
input clock. The Phase Locked Loop (PLL) module is a
wrapper around the PLL_ADV primitive that allows
the PLL to be used in the EDK tool suite.
Features
• Wrapper around the PLL_ADV primitive
• Full support for use with EDK 11.1 and later
versions
• Configurable BUFG insertion
• Configurable output delay adjustment for PPC
block clock insertion delay compensation in Virtex-
5 FXT parts
• Six output clocks with independently selectable
frequencies
LogiCORE™ Facts
Core Specifics
Supported Device
Family
Virtex^®-5, Spartan^®--6
Resources Used
I/O
LUTs FFs
Block
RAMs
N/A
N/A
N/A
N/A
Special Features
1 PLL Block
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
N/A
Verification
N/A
Instantiation Template
N/A
Additional Items
None
Design Tool Requirements
Xilinx Implementation
Tools
ISE^® 11.1 or later
Verification
N/A
Simulation
N/A
Synthesis
N/A
Support
Provided by Xilinx, Inc.
© 2007-2009 Xilinx, Inc. Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE and other designated brands included herein are trademarks of Xilinx in the United
States and other countries. All other trademarks are the property of their respective owners.
DS622 June 24, 2009
www.xilinx.com
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Product Specification