DS782 Datasheet, PDF (6/7 Pages) Xilinx, Inc – Has a user-selectable number of Spartan-6 GTP transceivers

ChipScope IBERT for Spartan-6 GTP
List of Acronyms
Table 2: List of Acronyms
Acronym
Definition
DRP
Dynamic Reconfiguration Port
FF
Flip-Flop
FPGA
Field Programmable Gate Array
I/O
Input/Output
IBERT
Integrated Bit Error Radio Tester
IP
Intellectual Property
ISE
Integrated Software Environment
JTAG
Joint Test Action Group
LUT
Lookup Table
PCS
Physical Coding Sublayer
PLL
Phase-Locked Loop
PMA
Physical Medium Attachment
PRBS
Pseudorandom binary sequence
RAM
Random Access Memory
RX
Receive
TX
Transmit
XST
Xilinx Synthesis Technology
Revision History
The following table sumarizes the change history for this document:
Date
09/16/2009
10/19/2011
Version
1.0
2.0
Description of Revisions
Release 11.3 (Initial Xilinx release).
• Updated to 2.02.a core version and 13.3 Xilinx tools.
• Added new section for generating the IBERT core.
• Added List of Acronyms.
• Updated Notice of Disclaimer and Copyright notice.
• Replaced “MGT” with “serial transceiver”
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DS782 October 19, 2011
www.xilinx.com
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Product Specification