DS782 Datasheet, PDF (4/7 Pages) Xilinx, Inc – Has a user-selectable number of Spartan-6 GTP transceivers

ChipScope IBERT for Spartan-6 GTP
IBERT needs a clock for the internal communication logic. This can come from an external pin, or from the
TXOUTCLK of one of the GTP transceivers enabled in the IBERT design. To use a clock from a pin, enable the Use
External Clock source radio button, type the frequency in the Frequency field, type the pin location in the Pin
Location field, and choose the Pin Input Standard. For differential standards, specify the P pin location.
To specify an internal clock, disable the Use External Clock source radio button in the first panel. In the System
Clock Source panel, specify the GTP transceiver in the GTP Dual Source combo box.
Generating the Design
After entering the IBERT core parameters, click Next to view the IBERT Design Summary. This includes the GTP
transceivers used, system clock, and the details of the global clock resources. To generate the design, click Generate.
Pattern Generation and Checking
Each serial transceiver enabled in the IBERT design has both a pattern generator and a pattern checker. The pattern
generator sends data out through the transmitter. The pattern checker takes the data coming in through the receiver
and checks it against an internally generated pattern. IBERT offers PRBS 7-bit, PRBS 15-bit, PRBS 23-bit, PRBS31-bit,
Clk 2x (101010...) and Clk 10x(11111111110000000000...) patterns. These patterns are optimized for the FPGA logic
width chosen, and are selectable at run time. The TX pattern and RX pattern are individually selectable.
The pattern checker logic also generates a ‘link’ signal that displays in the Analyzer software. The channel is linked
when there are five consecutive cycles of data with no errors. The incoming data is compared against a pattern that
is generated internally. When the checker receives five consecutive cycles of data with errors, it removes the channel
link. Internal counters accumulate the number of words and error received.
DRP and Ports Access
IBERT also provides flexibility to change serial transceiver ports and attributes. DRP interface logic is included that
allows the run-time software to monitor and change any attribute in any of the serial transceivers included in the
IBERT core. Readable and writable (when applicable) registers are also included that are connected to the various
ports of the serial transceiver. All are accessible at run time using the ChipScope Analyzer tool.
System Clock
The IBERT Core requires a free-running system clock to clock the communication and other logic included in the
IBERT core. This clock can be chosen at generation time to come from an FPGA pin, or be driven from the
TXOUTCLK port of one of the serial transceivers in the core. If the system clock is running faster than 150 MHz, it
is divided down internally using an DCM to satisfy timing constraints.
Interface Ports
The Input/Output (I/O) signals of the IBERT core consist only of the serial transceiver reference clocks, the serial
transceiver transmit and receive pins, and a system clock (optional).
Table 1: Interface Ports
Port Name
Direction
Description
SYSCLK
IN
Design clock that clocks all communication logic. This port is optional, because you can
select an internal serial transceiver clock at generation time to perform this function.
TXN[n-1:0], TXP[n-1:0]
OUT Transmit differential pairs for each of the n serial transceivers used.
DS782 October 19, 2011
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Product Specification