DS782 Datasheet, PDF (1/7 Pages) Xilinx, Inc – Has a user-selectable number of Spartan-6 GTP transceivers

DS782 October 19, 2011
ChipScope Integrated
Bit Error Ratio Test (IBERT)
for Spartan-6 GTP (v2.02a)
Product Specification
Introduction
The Xilinx ChipScope™ Pro IBERT core for Spartan®-6
GTP transceivers is customizable and can be used to
evaluate and monitor Spartan-6 GTP transceivers. The
design includes pattern generators and checkers
implemented in FPGA logic, and access to the ports and
the DRP attributes of the transceivers. Communication
logic is also included to allow the design to be run-time,
and is accessible through JTAG pins. The IBERT core is
a self-contained design; when generated, it runs
through the entire implementation flow, including
bitstream generation.
Features
• Provides a communication path between the
ChipScope Pro Analyzer software and the IBERT
core.
• Has a user-selectable number of Spartan-6 GTP
transceivers.
• Each transceiver can be customized for the desired
line rate, reference clock rate, reference clock
source, and datapath width.
• Requires a system clock that can be sourced from a
pin or one of the enabled serial transceivers.
LogiCORE IP Facts Table
Core Specifics
Supported
Device Family⁽¹⁾
Spartan-6
Supported User
Interfaces
Resources ⁽²⁾
N/A
Frequency
Configuration LUTs FFs I/O
Block
RAMs
Max. Freq
Config1
5921 9750 18
0
Provided with Core
139.567 MHz
Documentation
Design Files
Example Design
Test Bench
Constraints File
Product Specification
User Guide
Netlist
N/A
N/A
N/A
Simulation
Model
Tested Design Tools
Not Provided
Design Entry
Tools
Xilinx CORE Generator™ tool
Simulation
Not Provided
Synthesis Tools
Support
Not Provided
Provided by Xilinx @ www.xilinx.com/support
1. Including the variants of this FPGA device.
2. For single-serial transceiver design with 20-bit FPGA logic width.
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DS782 October 19, 2011
www.xilinx.com
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Product Specification