DS782 Datasheet, PDF (2/7 Pages) Xilinx, Inc – Has a user-selectable number of Spartan-6 GTP transceivers

ChipScope IBERT for Spartan-6 GTP
Applications
The IBERT core is designed to be used in any application that requires verification or evaluation of Spartan-6 GTP
transceivers.
Functional Description
The IBERT core provides a broad-based Physical Medium Attachment (PMA) evaluation and demonstration
platform for Spartan-6 GTP Transceivers. Parameterizable to use different serial transceivers and clocking
topologies, the IBERT core can also be customized to use different line rates, reference clock rates, and FPGA logic
widths. Data pattern generators and checkers are included for each serial transceiver desired, giving a variety of
different PRBS and clock patterns to be sent over the channels. In addition, the configuration and tuning of the serial
transceivers is accessible though logic that communicates to the DRP port of the serial transceiver, in order to
change attribute settings, as well as registers that control the values on the ports. At run time, the ChipScope
Analyzer tool communicates to the IBERT core through JTAG, using the Xilinx cables and proprietary logic that is
part of the IBERT core.
Serial Transceiver Features
IBERT is designed for PMA evaluation and demonstration. All the major PMA features of the serial transceiver are
supported and controllable in IBERT, including:
• Transmit (TX) pre-emphasis and post-emphasis
• TX differential swing
• Receive (RX) equalization
• Phase-Locked Loop (PLL) Divider settings
Some of the Physical Coding Sublayer (PCS) features offered by the transceiver are outside the scope of IBERT,
including
• Clock Correction
• Channel Bonding
• 8B/10B, 64B/66B, or 64B/67B encoding
• TX or RX Buffer Bypass
Generating the Core
Using the Xilinx CORE Generator™ software, you can define and generate a customized IBERT core for Spartan-6
FPGA GTP transceivers. When all the IBERT parameters have been chosen, a full design is generated, including a
bitstream. The IBERT core cannot be included in your design; it can only be generated in its own stand-alone design.
The ISE tools are invoked by the CORE Generator tool to generate a bitstream file (.bit) rather than a design netlist
file (.ngc or .edn).
1. In the Debug & Verification > ChipScope Pro IP category of CORE Generator, select IBERT Spartan6 GTP
(ChipScope Pro - IBERT) core.
2. Then click Customize in the right side of the window.
DS782 October 19, 2011
www.xilinx.com
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Product Specification