DS444 Datasheet, PDF (6/7 Pages) Xilinx, Inc – IP Processor Block RAM

IP Processor Block RAM (BRAM) Block (v1.00a)
Table 5: Supported BRAM Memory sizes for Virtex-5 and Virtex-6 FPGAs
Native Data
Width Size
(bits)
Supported Memory
Sizes (Bytes) /
BRAM Memory
Configuration
(Depth x Width)
Number of
BRAM
primitives
(36Kbit ea.)
required
Number of
BRAM_Addr
bits required
Typical BRAM_Addr(0:31)
bit usage for 64-bit wide
Memory (8 byte lanes)
C_NATIVE_DWIDTH = 32
32
4K / (1,024x32)
1 ⁽¹⁾
10
BRAM_Addr(20:29)
32
8K / (2,048x32)
2
11
BRAM_Addr(19:29)
32
16K / (4,096x32)
4
12
BRAM_Addr(18:29)
32
32K / (8,192x32)
8
13
BRAM_Addr(17:29)
32
64K / (16,384x32)
16
14
BRAM_Addr(16:29)
32
128K / (32,768x32)
32
15
BRAM_Addr(15:29)
32
256K / (65,536x32)
64
16
BRAM_Addr(14:29)
C_NATIVE_DWIDTH = 64
64
8K / (1,024x64)
2 ⁽¹⁾
10
BRAM_Addr(19:28)
64
16K / (2,048x64)
4
11
BRAM_Addr(18:28)
64
32K / (4,096x64)
8
12
BRAM_Addr(17:28)
64
64K / (8,192x64)
16
13
BRAM_Addr(16:28)
64
128K / (16,384x64)
32
14
BRAM_Addr(15:28)
64
256K / (32,768x64)
64
15
BRAM_Addr(14:28)
64
512K / (65,536x64)
128
16
BRAM_Addr(13:28)
C_NATIVE_DWIDTH = 128
128
16K / (1,024x128)
4 ⁽¹⁾
10
BRAM_Addr(18:27)
128
32K / (2,048x128)
8
11
BRAM_Addr(17:27)
128
64K / (4,096x128)
16
12
BRAM_Addr(16:27)
128
128K / (8,192x128)
32
13
BRAM_Addr(15:27)
128
256K / (16,384x128)
64
14
BRAM_Addr(14:27)
128
512K / (32,768x128)
128
15
BRAM_Addr(13:27)
128
1024K / (65,536x128)
256
16
BRAM_Addr(12:27)
Notes:
1. Virtex-5 and Virtex-6 BRAM primitives have up to 4 byte enables per primitive.
Specification Exceptions
Not applicable.
Reference Documents
None
6
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DS444 March 1, 2011
Product Specification