DS444 Datasheet, PDF (2/7 Pages) Xilinx, Inc – IP Processor Block RAM

IP Processor Block RAM (BRAM) Block (v1.00a)
Functional Description
The BRAM Block is a structural design that instantiates a number of RAMB primitives, depending on
specific factors. An example is shown in Figure 1.
X-Ref Target - Figure 1
port_A[0 to 7]
port_B[0 to 7]
RAMB16_s8_s8
port_A[0 to 31]
port_A[0 to 7]
port_A[0 to 7]
RAMB16_s8_s8
RAMB16_s8_s8
port_B[0 to 7]
port_B[0 to 7]
port_A[0 to 7]
port_B[0 to 7]
RAMB16_s8_s8
ds444_01
Figure 1: Example of BRAM Block Implementation with Four RAMB16 Primitives
BRAM Block I/O Signals
The I/O signals for the BRAM Block are shown in Figure 1 and described in Table 1. Note that the data
in/out signals are named the opposite of their actual direction. This is because the signals are refer-
enced from the point of view of the BRAM controller so that “data in” on the controller connects to
“data in” on the BRAM block, and “data out” on the controller connects to “data out” on the BRAM
block.
Table 1: BRAM Block I/O Signals
Signal Name
Interface
I/O
Initial
State
Description
BRAM_Rst_A
Port A
I
BRAM Reset, Active High
BRAM_Clk_A
Port A
I
BRAM Clock
BRAM_EN_A
Port A
I
BRAM Enable, Active High
BRAM_WEN_A
Port A
I
BRAM Write Enable, Active High
BRAM_Addr_A
(0:C_PORT_AWIDTH-1)
Port A
I
BRAM Address
BRAM_Din_A
(0:C_PORT_DWIDTH-1)
Port A
O
BRAM Data Output. Note signal name is referenced
0 from the point of view of the controller (on which it is
an input).
BRAM_Dout_A
(0:C_PORT_DWIDTH-1)
Port A
I
BRAM Data Input. Note signal name is referenced
from the point of view of the controller (on which it is
an output).
BRAM_Rst_B
Port B
I
BRAM Reset, Active High
BRAM_Clk_B
Port B
I
BRAM Clock
BRAM_EN_B
Port B
I
BRAM Enable, Active High
BRAM_WEN_B
Port B
I
BRAM Write Enable, Active High
2
www.xilinx.com
DS444 March 1, 2011
Product Specification