DS444 Datasheet, PDF (1/7 Pages) Xilinx, Inc – IP Processor Block RAM

DS444 March 1, 2011
IP Processor Block RAM
(BRAM) Block (v1.00a)
Product Specification
Introduction
The BRAM Block is a configurable memory module
that attaches to a variety of BRAM Interface Control-
lers.
The BRAM Block structural HDL is generated by the
EDK design tools based on the configuration of the
BRAM interface controller IP. All BRAM Block parame-
ters are automatically calculated and assigned by the
Platgen and Simgen EDK tools.
Features
 Fully automated generation and configuration of
HDL through EDK Platgen and Simgen tools.
 Number of BRAM primitives utilized is a function
of the configuration parameters for: memory
address range, number of byte-write enables, the
data width, and the targeted architecture
 Both Port A and Port B of the memory block can be
connected to independent BRAM Interface
Controllers: LMB (Local Memory Bus), PLB
(Processor Local Bus), and OCM (On-Chip
Memory).
 Supports byte, half-word, word, and
doubleword transfers provided the correct
number of byte-write enables have been
configured
LogiCORE IP Facts
Supported Device
Family
Core Specifics
Spartan^®-3A/3A DSP, Spartan-3,
Spartan-3E, Automotive
Spartan 3/3E/3A/3A DSP, Spartan-6,
Virtex^®-4 /4Q/4QV, Virtex-5/5FX,
Virtex-6/6CX
Resources Used
I/O
LUTs FFs
Block
RAMs
n
n
n
n
Special Features
Add if applicable
Provided with Core
Documentation
Product Specification
Design File Formats
VHDL
Constraints File
.ucf (user constraints file)
Verification
VHDL Test Bench
Instantiation Template
VHDL Wrapper
Additional Items
N/A
Design Tool Requirements
Xilinx Implementation
Tools
ISE® 12.1
Verification
Mentor Graphics ModelSim: v6.5c
and above
Simulation
Mentor Graphics ModelSim: v6.5.c
and above
Synthesis
XST
Support
Provided by Xilinx, Inc.
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DS444 March 1, 2011
www.xilinx.com
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Product Specification