DS444 Datasheet, PDF (3/7 Pages) Xilinx, Inc – IP Processor Block RAM

IP Processor Block RAM (BRAM) Block (v1.00a)
Table 1: BRAM Block I/O Signals (Cont’d)
Signal Name
Interface
I/O
Initial
State
Description
BRAM_Addr_B
(0:C_PORT_AWIDTH-1)
Port B
I
BRAM Address
BRAM_Din_B
(0:C_PORT_DWIDTH-1)
Port B
O
BRAM Data Output. Note signal name is referenced
0 from the point of view of the controller (on which it is
an input).
BRAM_Dout_B
(0:C_PORT_DWIDTH-1)
Port B
I
BRAM Data Input. Note signal name is referenced
from the point of view of the controller (on which it is
an output).
BRAM Block Parameters
Table 2: BRAM block Parameters
Parameter
Name
Feature/Description
Allowable Values
C_PORT_
AWIDTH
Port A and B Address Width 9 – 17
C_PORT_
DWIDTH
Port A and B Data Width
32, 64, 128
C_NUM_WE
Number of Write Enables (Byte
Enables for Write)
1, 2, 4, 8, 16
C_FAMILY
Target FPGA family of
bram_block
spartan3, spartan3e,
spartan3a, spartan3adsp,
aspartan3, aspartan3e,
aspartan3a,
aspartan3adsp,spartan6,
virtex4, qvirtex4, qvvirtex4,
virtex5, virtex5fx, virtex6,
virtex6cx
C_MEMSIZE Size of BRAM(s) in bytes
2048 - 524288
Tool
Calculated
VHDL Type
Yes
integer
Yes
integer
Yes
integer
Yes
string
Yes
integer
Allowable Parameter Combinations
For architectures that support the RAMB16 primitive, the minimum value for C_MEMSIZE is 8192
(8kB) and the maximum value is 262144 (256kB).
For architectures that support the RAMB16BWE primitive, the minimum value for C_MEMSIZE is
2048 (2kB) and the maximum value is 262144 (256kB).
For architectures that support the RAMB36 primitive, the minimum value for C_MEMSIZE is 4096
(4kB) and the maximum value is 524288 (512kB).
Parameter - Port Dependencies
The width of many of the BRAM Block signals depends on the number of memories in the system and
the width of the various data and address buses. The dependencies between the BRAM design param-
eters and I/O signals are shown in Table 3.
DS444 March 1, 2011
www.xilinx.com
3
Product Specification