DS444 Datasheet, PDF (4/7 Pages) Xilinx, Inc – IP Processor Block RAM

IP Processor Block RAM (BRAM) Block (v1.00a)
Table 3: Parameter-Port Dependencies
Name
Affects
Depends
Relationship Description
Design Parameters
C_PORT_
DWIDTH
BRAM_Din_A/B 0 to C_PORT_DWIDTH -1 Width of BRAM interface
BRAM_Dout_A/B 0 to C_PORT_DWIDTH -1 Width of BRAM interface
C_PORT_
AWDITH
BRAM_Addr_A/B 0 to C_PORT_AWIDTH -1 Width of the BRAM Address Bus
C_NUM_WE
BRAM_WEN_A/B 0 to C_NUM_WE -1
Number of byte enable signals
I/O Signals
BRAM_Addr_A
C_PORT_AWIDTH
Width varies with the width of the BRAM
Address Bus
BRAM_Din_A
C_PORT_DWIDTH
Width varies with the width of the BRAM
Data Bus
BRAM_Dout_A
C_PORT_DWIDTH
Width varies with the width of the BRAM
Data Bus
BRAM_WEN_A
C_NUM_WE
Width varies with the number of byte-
write enable signals
BRAM_Addr_B
C_PORT_AWIDTH
Width varies with the width of the BRAM
Address Bus.
BRAM_Din_B
C_PORT_DWIDTH
Width varies with the width of the BRAM
Data Bus.
BRAM_Dout_B
C_PORT_DWIDTH
Width varies with the width of the BRAM
Data Bus.
BRAM_WEN_B
C_NUM_WE
Width varies with the number of byte-
write enable signals
Design Implementation
Design Tools
The BRAM Block design is generated by the EDK tools.
XST is the synthesis tool used for synthesizing the BRAM Block. The EDIF netlist output from XST is
then input to the Xilinx Alliance tool suite for actual device implementation.
The BRAM Block is a structural design that instantiates a number of RAMB primitives. The number of
block RAM primitives instantiated in a BRAM Block depends on the following factors
 Each primitive is either 4kb or 16kb depending on architecture. The address range
(C_PORT_AWIDTH) times the accessed data width (C_PORT_DWIDTH) defines the total number
of bits required.
 Instantiated RAMB primitives can be configured to have at most a 32 bit wide data interface. Thus
a 64 bit interface will require at least 2 BRAM primitives in parallel.
 RAMB primitive in architectures prior to Virtex-4 only have a single write enable per port. Thus if
byte-write enable is required on a 32 bit data port (C_NUM_WE=4), these architectures will use a
minimum of 4 BRAM primitives.
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DS444 March 1, 2011
Product Specification