DS444 Datasheet, PDF (5/7 Pages) Xilinx, Inc – IP Processor Block RAM

IP Processor Block RAM (BRAM) Block (v1.00a)
Target Technology
The target technology is an FPGA listed in the Supported Device Family field of the LogiCORE Facts
table.
Device Utilization and Performance Benchmarks
The device utilization depends on the configured BRAM Block size in relation to the RAMB primitive
resources of the targeted device. See the user guide for the respective FPGA family for details on RAMB
primitive performance and available resources.
Supported BRAM Memory Configurations
Typical BRAM memory configurations that are supported by this BRAM Controller are: For Virtex-4,
Spartan-3, and Spartan-6 devices, see Table 4. For Virtex-5 and Virtex-6 devices, see Table 5. The BRAM
instantiations are not provided by this core. They are part of the bram_block module generated by
the EDK XPS tools during embedded system creation.
Table 4: Supported BRAM Memory sizes for Virtex-4, Spartan-3, and Spartan-6 FPGAs
Native Data
Width Size
(bits)
Supported Memory
Sizes (Bytes) /
BRAM Memory
Configuration
(Depth x Width)
Number of
BRAM
primitives
(18Kbit ea.)
required
Number of
BRAM_Addr
bits required
Typical BRAM_Addr(0:31)
bit usage for BRAM width
C_PORT_DWIDTH = 32
32
8K / (2,048x32)
4 ⁽¹⁾
11
32
16K / (4,096x32)
8
12
BRAM_Addr(17:29)
BRAM_Addr(16:29)
32
32K / (8,192x32)
16
13
BRAM_Addr(15:29)
32
64K / (16,384x32)
32
14
BRAM_Addr(14:29)
C_PORT_DWIDTH = 64
64
16K / (2,048x64)
8 ⁽²⁾
11
BRAM_Addr(18:28)
64
32K / (4,096x64)
16
12
BRAM_Addr(17:28)
64
64K / (8,192x64)
32
13
BRAM_Addr(16:28)
64
128K / (16,384x64)
64
14
BRAM_Addr(15:28)
C_PORT_DWIDTH = 128
128
32K / (2,048x128)
16 ⁽³⁾
11
BRAM_Addr(16:27)
128
64K / (4,096x128)
32
12
BRAM_Addr(15:27)
128
128K / (8,192x128)
64
13
BRAM_Addr(14:27)
128
256K / (16,384x128)
128
14
BRAM_Addr(13:27)
Notes:
1. A minimum of 4 BRAM primitives are required to maintain byte write capability for a 32-bit native data width
BRAM array.
2. A minimum of 8 BRAM primitives are required to maintain byte write capability for a 64-bit native data width
BRAM array.
3. A minimum of 16 BRAM primitives are required to maintain byte write capability for a 128-bit native data width
BRAM array.
DS444 March 1, 2011
www.xilinx.com
5
Product Specification