XQ4000E Datasheet, PDF (3/36 Pages) Xilinx, Inc – System Performance beyond 60 MHz

R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E Recommended Operating Conditions^(1,2)
Symbol
Description
Min
Max
V_CC
V_IH
Supply voltage relative to GND, T_J = –55°C to +125°C
Supply voltage relative to GND, T_C = –55°C to +125°C
High-Level Input Voltage
Plastic
Ceramic
TTL inputs
CMOS inputs
4.5
4.5
2.0
70%
5.5
5.5
V_CC
100%
V_IL
Low-Level Input Voltage
TTL inputs
0
CMOS inputs
0
0.8
20%
T_IN Input signal transition time
-
250
Notes:
1. At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.35% per °C.
2. Input and output measurement threshold are 1.5V for TTL and 2.5V for CMOS.
Units
V
V
V
V_CC
V
V_CC
ns
XQ4000E DC Characteristics Over Recommended Operating Conditions
Symbol
Description
Min
Max Units
V_OH High-level output voltage @ I_OH = –4.0 mA, V_CC min TTL outputs
2.4
-
V
High-level output voltage @ I_OH = –1.0 mA, V_CC min CMOS outputs V_CC – 0.5
-
V
V_OL Low-level output voltage @ I_OL = 12.0 mA, V_CC min⁽¹⁾ TTL outputs
-
0.4
V
CMOS outputs
-
0.4
V
I_CCO Quiescent FPGA supply current⁽²⁾
-
50
mA
I_L
Input or output leakage current
–10
+10
µA
C_IN Input capacitance (sample tested)
I_RIN Pad pull-up (when selected) at V_IN = 0V (sample tested)⁽³⁾
I_RLL Horizontal longline pull-up (when selected) at logic Low⁽³⁾
-
–0.02
0.2
16
pF
–0.25
mA
2.5
mA
Notes:
1. With 50% of the outputs simultaneously sinking 12 mA, up to a maximum of 64 pins.
2. With no output current loads, no active input or Longline pull-up resistors, all package pins at V_CC or GND, and the FPGA configured
with the development system Tie option.
3. Characterized Only.
DS021 (v2.2) June 25, 2000
www.xilinx.com
3
Product Specification
1-800-255-7778