XQ4000E Datasheet, PDF (23/36 Pages) Xilinx, Inc – System Performance beyond 60 MHz

R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX CLB RAM Synchronous (Edge-Triggered) Write Operation Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
All timing parameters assume worst-case operating condi-
tions (supply voltage and junction temperature). Values
apply to all XQ4000EX devices unless otherwise noted.
Symbol
Single Port RAM
Write Operation
T_WCS
Address write cycle time (clock K period)
T_WCTS
T_WPS
Clock K pulse width (active edge)
T_WPTS
T_ASS
Address setup time before clock K
T_ASTS
T_AHS
Address hold time after clock K
T_AHTS
T_DSS
DIN setup time before clock K
T_DSTS
T_DHS
DIN hold time after clock K
T_DHTS
T_WSS
WE setup time before clock K
T_WSTS
T_WHS
WE hold time after clock K
T_WHTS
T_WOS
Data valid after clock K
T_WOTS
Notes:
1. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
Size
-4
Min Max
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
16x2
32x1
11.0
-
11.0
-
5.5
-
5.5
-
2.7
-
2.6
-
0
-
0
-
2.4
-
2.9
-
0
-
0
-
2.3
-
2.1
-
0
-
0
-
-
8.2
-
10.1
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Dual-Port RAM Synchronous (Edge-Triggered) Write Operation Characteristics
Symbol
Dual Port RAM
Size⁽¹⁾
-4
Min Max
Write Operation
T_WCDS
Address write cycle time (clock K period)
T_WPDS
Clock K pulse width (active edge)
T_ASDS
Address setup time before clock K
T_AHDS
Address hold time after clock K
T_DSDS
DIN setup time before clock K
T_DHDS
DIN hold time after clock K
T_WSDS
WE setup time before clock K
T_WHDS
WE hold time after clock K
T_WODS
Data valid after clock K
Notes:
1. Timing for the 16x1 RAM option is identical to 16x2 RAM timing.
2. Applicable Read timing specifications are identical to Level-Sensitive Read timing.
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
16x1
11.0
5.5
-
3.1
-
0
-
2.9
-
0
-
2.1
-
0
-
-
9.4
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
DS021 (v2.2) June 25, 2000
www.xilinx.com
23
Product Specification
1-800-255-7778