XQ4000E Datasheet, PDF (15/36 Pages) Xilinx, Inc – System Performance beyond 60 MHz

R
QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4000E IOB Input Switching Characteristic Guidelines (continued)
-3
-4
Symbol
Description
Device
Min Max Min Max Units
Setup Times (TTL Inputs)^(1,2)
T_PICK Pad to clock (IK), no delay
T_PICKD Pad to clock (IK), with delay
All devices 2.6
-
4.0
-
ns
XQ4005E
-
-
10.9
-
ns
XQ4010E 9.8
-
11.3
-
ns
XQ4013E 10.2
-
11.8
-
ns
XQ4025E
-
-
14.0
-
ns
Setup Times (CMOS Inputs)^(1,2)
T_PICKC Pad to clock (IK), no delay
T_PICKDC Pad to clock (IK), with delay
All devices 3.3
-
6.0
-
ns
XQ4005E
-
-
12.0
-
ns
XQ4010E 10.5
-
13.0
-
ns
XQ4013E 10.9
-
13.5
-
ns
XQ4025E
-
-
16.0
-
ns
(TTL or CMOS)
T_ECIK Clock enable (EC) to clock (IK), no delay
T_ECIKD Clock enable (EC) to clock (IK), with delay
All devices 2.5
-
3.5
-
ns
XQ4005E
-
-
10.4
-
ns
XQ4010E 9.7
-
10.7
-
ns
XQ4013E 10.1
-
11.1
-
ns
XQ4025E
-
-
14.0
-
ns
Global Set/Reset⁽³⁾
T_RRI Delay from GSR net through Q to I1, I2
All devices -
7.8
-
12.0 ns
T_MRW GSR width
All devices 11.5
-
13.0
-
ns
T_MRI GSR inactive to first active clock (IK) edge
All devices 11.5
-
13.0
-
ns
Notes:
1. Input pad setup and hold times are specified with respect to the internal clock (IK). For setup and hold times with respect to the clock
input pin, see the pin-to-pin parameters in the Guaranteed Input and Output Parameters table.
2. Voltage levels of unused pads, bonded or unbonded, must be valid logic levels. Each can be configured with the internal pull-up
(default) or pull-down resistor, or configured as a driven output, or can be driven from an external source.
3. Timing is based on the XC4005E. For other devices see the XACT timing calculator.
DS021 (v2.2) June 25, 2000
www.xilinx.com
15
Product Specification
1-800-255-7778