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XQ4000E Datasheet, PDF (29/36 Pages) Xilinx, Inc – System Performance beyond 60 MHz
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QPRO XQ4000E/EX QML High-Reliability FPGAs
XQ4028EX IOB Input Switching Characteristic Guidelines
Testing of switching parameters is modeled after testing
methods specified by MIL-M-38510/605. All devices are
100% functionally tested. Internal timing parameters are
derived from measuring internal test patterns. Listed below
are representative values. For more specific, more precise,
and worst-case guaranteed data, use the values reported
by the static timing analyzer (TRCE in the Xilinx Develop-
ment System) and back-annotated to the simulation netlist.
These path delays, provided as a guideline, have been
extracted from the static timing analyzer report. All timing
parameters assume worst-case operating conditions (sup-
ply voltage and junction temperature). Values apply to all
XQ4000EX devices unless otherwise noted.
-4
Symbol
Description
Min
Units
Clocks
TOKIK Delay from FCL enable (OK) active to IFF clock (IK) active edge
Propagation Delays
3.2
ns
TPID
Pad to I1, I2
TPLI
Pad to I1, I2 via transparent input latch, no delay
TPPLI Pad to I1, I2 via transparent input latch, partial delay
TPDLI Pad to I1, I2 via transparent input latch, full delay
TPFLI Pad to I1, I2 via transparent FCL and input latch, no delay
TPPFLI Pad to I1, I2 via transparent FCL and input latch, partial delay
Propagation Delays (TTL Inputs)
2.2
ns
3.8
ns
13.3
ns
18.2
ns
5.3
ns
13.6
ns
TIKRI
Clock (IK) to I1, I2 (flip-flop)
TIKLI
Clock (IK) to I1, I2 (latch enable, active Low)
TOKLI FCL enable (OK) active edge to I1, I2 (via transparent standard input latch)
Global Set/Reset
3.0
ns
3.2
ns
6.2
ns
TMRW Minimum GSR pulse width
13.0
ns
TRRI
Delay from GSR input to any Q
22.8
ns
Notes:
1. FCL = Fast Capture Latch, IFF = Input Flip-Flop or Latch
2. For CMOS input levels, see the "XQ4028EX Input Threshold Adjustments" on page 28.
3. For setup and hold times with respect to the clock input pin, see the Global Low Skew Clock and Global Early Clock Setup and Hold
tables on page 28.
DS021 (v2.2) June 25, 2000
www.xilinx.com
29
Product Specification
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