UG445 Datasheet, PDF (22/24 Pages) –

Power, Sequencing, and Slew Rates
R
The following is sample code for how to achieve the fast rise in VHDL:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity top is
Port ( data : in std_logic; data_to_pin : inout std_logic);
end top;
architecture Behavioral of top is
begin
data_to_pin<= data when ((data and data_to_pin) ='0') else 'Z';
end Behavioral;
Code for Verilog:
module top(data, data_to_pin );
input data;
inout data_to_pin ;
assign data_to_pin = ((data & data_to_pin) == 0)? data : 1'bz;
endmodule
I/O Standards
The supported I/O standards for the different CPLD families are as follows:
• XC9500, XC9500XL, and XC9500XV: LVTTL, LVCMOS33
• CoolRunner XPLA3: LVCMOS33
• CoolRunner-II: LVTTL, LVCMOS33, LVCMOS25, LVCMOS18, LVCMOS15, HSTL_1,
SSTL2_1, SSTL3_1, and LVCMOS15 require use of Schmitt trigger inputs.
Simultaneous Switching Output Limits
Xilinx does not characterize the CPLD device packages to estimate the maximum number
of Simultaneous Switching Outputs (SSOs) before ground bounce. However, Xilinx
recommends that you not have more than 8 SSOs on the entire chip (all banks included).
If you need to have more than 8 SSOs, Xilinx recommends that you consider altering the
slew rate setting on these outputs to skew the outputs relative to each other. By following
this recommendation, you can avoid ground bounce due to SSOs.
Decoupling Guidelines
The minimum decoupling recommendations for CPLD devices are to provide both 0.1 and
0.01 uF capacitors at every V_CC point of the chip and attach them directly to the nearest
ground.
Schmitt Trigger
CoolRunner-II is the only family to have the Schmitt trigger feature. A Schmitt trigger is an
input circuit used to reduce noise on the input signal. In CoolRunner-II devices, there is a
Schmitt trigger available on all I/Os, but only with the I/O standards that do not require a
VREF.
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www.xilinx.com
CPLD I/O User Guide
UG445 (v1.2) January 14, 2014