UG445 Datasheet, PDF (18/24 Pages) –

Power, Sequencing, and Slew Rates
R
There are three basic scenarios:
• V_CCINT and V_CCIO rise together (both tied to the same 1.8V rail)
• V_CCIO before V_CCINT (I/O comes alive before logic)
• V_CCINT before V_CCIO (logic comes alive before I/O)
During configuration, the I/Os are placed in a Tristate condition with a weak pull-up to
V_CCIO. If V_CCIO voltage is either rising with V_CCINT or is well established before V_CCINT
begins rising (i.e., scenario 1 and 2), the I/Os will track V_CCIO before the logic that drives
the I/Os is active. This may be seen as Logic High to a downstream device. If the output
should be driving low at power-up, then the tracking of the I/O to V_CCIO might appear as
a glitch. However, this is the intended behavior as specified in the data sheet. An example
of the tracking of V_CCIO by the output is shown in Figure 4.
Figure 4: V_CCINT is powered after V_CCIO
UG445_03_111607
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CPLD I/O User Guide
UG445 (v1.2) January 14, 2014