UG445 Datasheet, PDF (20/24 Pages) –

Power, Sequencing, and Slew Rates
R
V_CCAUX is minimal. However, if you remove power from V_CCAUX, the state of the TAP
controller cannot be guaranteed.
Current Consumption
Programming is defined as the process of programming the non-volatile memory.
Configuration is defined as the process of the CPLD self-configuring upon power-up
(Tconfig).
Programming current:
• CoolRunner-II
Typical: 5 mA increasing up to 15 mA for the largest device (512 macro cell).
Max: 30 mA for the family.
• CoolRunner XPLA3
The current required for ISP programming is 30 mA. This information is taken from
the CoolRunner XPLA3 CPLD Data Sheet (DS012), see Programming Specifications
(I_CCP), Table 7.
• XC9500, XC9500XL, and XC9500XV
Tests show that the 95144XL requires approximately 16 mA.
Tests show that the 95288XL requires between 19 mA to 40 mA.
• Tconfig
Can be found in the device specific data sheet.
Leakage current is the amount of current consumed when the voltage at the pin is at one of
the rails, (i.e., either Logic High or Logic Low). This is specified in the density specific data
sheets (IL).
Crowbar current is the amount of current consumed when both the “p” and the “n”
transistor are on and there is a path from V_CCIO to ground; this is when the voltage at the
pin is in between the voltage rails.
The amount of crowbar current is not specified by Xilinx, as the transition rate plays a large
role in the amount of current.
5V Tolerance
CoolRunner XPLA3 devices are 5V-tolerant. Also, the XC9500, XC9500XL, and XC9500XV
families are 5V-tolerant.
CoolRunner-II devices are not 5V-tolerant. The 5V Tolerance Techniques for CoolRunner-II
Devices Application Note (XAPP429) discusses methods of adding external circuitry to allow
CoolRunner-II to operate in a 5V environment. If you drive 5V into the CoolRunner-II, the
long-term reliability of the device is compromised. Below is an equation to estimate how
the reliability is affected (this is strictly for illustrative purposes). Customers should not
exceed the recommended operating conditions given in the device data sheet.
• I/O Gate Oxide Lifetime to be:
Lifetime = C₀10^–βE exp (E_a ⁄ KT)
• Based on the above equation, Oxide Lifetime at 5.0V is 3313X smaller than Lifetime at
3.3V
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CPLD I/O User Guide
UG445 (v1.2) January 14, 2014