UG445 Datasheet, PDF (2/24 Pages) –

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Revision History
The following table shows the revision history for this document.
Date
6/26/2007
11/27/2007
01/14/2014
Version
1.0
1.1
1.2
Revision
Initial Xilinx release.
• Added “JTAG Termination,” page 12.
• Updated Figure 4.
• Added sentence at the end of first paragraph after Figure 5.
JTAG pin information changed in “JTAG Termination,” page 12. Values in “Maximum
I/O Power Dissipation,” page 15 under “When sourcing 40 mA, the voltage at the
output of the CPLD will be 2.3V...” changed.
CPLD I/O User Guide
www.xilinx.com
UG445 (v1.2) January 14, 2014