UG445 Datasheet, PDF (19/24 Pages) –

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Power, Sequencing, and Slew Rates
Figure 5: V_CCINT is powered before V_CCIO
UG445_04_052207
For best results (with multiple power rails), Xilinx recommends that V_CCINT be applied
before V_CCIO (see Figure 5); this ensures that the internal logic is correct before the I/Os are
active. If V_CCIO is powered before V_CCINT, this does not damage the device, but there
might be glitches on the I/O as the internal circuitry is initialized. Xilinx recommends not
leaving V_CCIO floating while V_CCINT is ramping.
During power-up, all Xilinx CPLDs employ internal circuitry which keeps the devices in
the quiescent state (weak pull-up) until the V_CCINT supply voltage is at a safe level.
The approximate “safe level” for each device is listed below:
• CoolRunner-II: 1.3V
• CoolRunner XPLA3: 2.1V
• XC9500XL: 2.5V
• XC9500XV: 1.9V
• XC9500: 3.8V
V_CCIO can be removed without damaging the part, but the exact behavior under these
conditions is not characterized, and therefore, not recommended. When power is removed
from V_CCIO with the core powered, the I/Os still try to drive and read their pins.
Transistors are in an unknown state, which results in more current than if the I/Os were
disabled or held in a known state.
V_CCIO is not required for programming of the non-volatile memory of a CoolRunner-II.
However, it is strongly recommended to power V_CCIO during programming. For the
XC9500, XC9500XL, XC9500XV, and CoolRunner XPLA3 devices, V_CCIO is required for
configuration and programming.
V_CCAUX is used to power the JTAG circuitry. This leads to a common question, can V_CCAUX
be safely removed after configuration. This is not recommend. V_CCAUX should be powered
even after configuration. If there are no JTAG instructions, the power consumed on
CPLD I/O User Guide
www.xilinx.com
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UG445 (v1.2) January 14, 2014