X88C75 Datasheet, PDF (8/27 Pages) Xicor Inc. – Port Expander and E2 Memory

X88C75 SLIC^® E²
BITS 7:6
Setting these two bits to any combination other than “00”
or “11” will interfere with device proper operation.
E² Memory Map Register (EEM)
Default = 08
7
6
5
4
3
2
1
0
0
0 LAM 0 RST A15 A14 A13
2887 ILL F11
A15-A13
Modifying these three bits changes the location of the
program memory within the address map.The A15-A13
correspond to the upper three address bits of the 8K-
byte page where program memory will be mapped.
RST
The RST bit controls the polarity of the RESET input pin.
“0” = RESET is Active LOW
“1” = RESET is Active HIGH
LAM
Port B can be configured as either a general purpose
I/O port (normal I/O mode), or latched address mode
(LAM). The LAM option programs port B to output the
demultiplexed low order byte of the address latched into
the X88C75 by ALE. The LAM bit selects between these
two modes.
“0” = PORT B is I/O Port
“1” = Port B outputs low address byte (A7-A0)
Setting the Mapping Registers
The mapping registers are written using a modified
version of the Software Data Protection sequence. All
timings must adhere to the normal Software Data Pro-
tection sequence.
The complemented contents of the SFR map register
and the E² memory map register can be read by the
microcontroller at their corresponding SFR addresses.
The physical memory location of these registers can be
derived by adding the following offset to the SFR base
address:
SFR Map Register
00H
E² Memory Map Register
38H
If the regions specified in the map registers overlap, only
the SFR will be accessible.
Figure 8. Setting the SFR Map Register
AA
b2 b1 b0 P 555
55
b2 b1 b0 P AAA
A0
b2 b1 b0 P 555
AA
b2 b1 b0 P 555
D0
b2 b1 b0 P AAA
Desired
Value
b2 b1 b0 P XXX
Delay of t_WC
Exit Routine
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
2887 ILL F12.1
Figure 9. Setting Program Memory Map Register
AA
b2 b1 b0 P 555
55
b2 b1 b0 P AAA
A0
b2 b1 b0 P 555
AA
b2 b1 b0 P 555
E0
b2 b1 b0 P AAA
Desired
Value
b2 b1 b0 P XXX
Delay of t_WC
Exit Routine
X = Don’t Care
B[2:0] = E2M [2:0]
P = Address bit (A12) of the
memory plane not being read.
2887 ILL F13.1
8