X88C75 Datasheet, PDF (2/27 Pages) Xicor Inc. – Port Expander and E2 Memory

X88C75 SLIC^® E²
which allows Individual blocks of the memory to be
configured as read-only or read/write.
Each bidirectional port consists of 8 general purpose
I/O lines and 1 data strobe line. The ports also feature a
configurable interrupt request output.
Access to the X88C75 is accomplished through the
multiplexed address/data bus of the 80C51 type control-
lers. An internal programmable address decoder maps
the internal memory and register locations into the
desired address space.
ARCHITECTURAL OVERVIEW
The X88C75 incorporates the interface circuitry nor-
mally needed to decode the control signals and
demultiplex the address/data bus to provide a “seam-
less” interface.
The control inputs on the X88C75 are configured such
that it is possible to directly connect them to the proper
interface signals of the 80C51 microcontroller. The
reading of data from the chip is controlled either by the
PSEN or the RD signal, which essentially maps the
X88C75 into both the Program and the Data Memory
address map.
Reading and writing of the nonvolatile memory array is
analogous to RAM operation. During a write operation to
either the nonvolatile memory or the control registers,
ALE latches the address to be written into the X88C75.
The rising edge of WR latches the data to be written.
The nonvolatile memory of the X88C75 is internally
organized as two independent arrays of 4K-bytes with
the A12 input selecting which of the two planes of
memory is to be accessed. While the processor is
executing code out of one plane, write operations can
take place in the other plane; allowing the processor to
continue execution of code out of the X88C75 during a
byte or page write to the device. This feature is called
Concurrent Read During Write.
The X88C75 also features an advanced implementation
of the Software Data Protection scheme, called Block
Lock Protect, which allows the nonvolatile memory array
to be treated as 8 independent sections of 1K-bytes.
Each of these sections can be independently enabled
for write operations. This allows segmentation of the
memory contents into writable and non-writable sec-
tions, thereby, allowing certain sections of the device to
be secured so that updates can only occur in a controlled
environment. (e.g. in an automotive application, only at
FUNCTIONAL DIAGRAM
A0–A15
ADDRESS
LATCH
I/O0–I/O7
I/O
BUFFER
&
LATCH
CE
WR
RD
ALE
PSEN
WC
RESET
IRQ
MASTER
CONTROL
LOGIC
LEFT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
DATA I/O BUS
RIGHT PLANE
DECODE
1K X 8
1K X 8
E2PROM
1K X 8
1K X 8
16 X 8
GENERAL
PURPOSE
REGISTERS
PORT SELECT
PORT
A
PORT
B
SDP
DECODE
MEM. MAP
CONFIG
REGISTER
PORT
SPECIAL
FUNCTION
REGISTERS
2887 ILL F03
2