X88C75 Datasheet, PDF (7/27 Pages) Xicor Inc. – Port Expander and E2 Memory

X88C75 SLIC^® E²
Figure 7. On-Chip Registers
76543210
FC00
0
0 A15 A14 A13 A12 A11 A10 ^SFRM*
Special Function Register
Memory Map Register
FC08 MSB
LSB ^{PDRB Port Data Register B}
FC10 MSB
LSB ^{PDRA Port Data Register A}
FC18 INT INTA INTB ENA ENB ENEE 0 EOW ISR
Interrupt Status Register
FC20 IRST 1 AWO BWO DIRA DIRB STRA STRB CR
Configuration Register
FC28 MSB
LSB ^{PPRB Port Pin Register B}
FC30 MSB
LSB ^{PPRA Port Pin Register A}
FC38
0
0 LAM 0 RST A15 A14 A13 ^EEM*
E² Memory Map Register
FE00 _MSB
LSB
16 Bytes General Purpose SRAM
FE0F MSB
LSB
NOTE: * The value returned by reading these registers is the complement of the
actual data. These registers are nonvolatile and a special SDP sequence
is used to alter their contents. All the other registers are initialized by a
valid reset input signal and when the device is power cycled.
2887 ILL F30.2
Programmable Address Decoding
The X88C75 features an internal programmable ad-
dress decoder which allows the nonvolatile memory
array and the internal registers to be mapped in various
locations of the 64K-byte memory map. The register set
is mappable into a 1K-byte block, while the nonvolatile
memory array is mappable into an 8K-byte block. The
mapping is controlled by two nonvolatile configuration
registers, the SFR Map Register and the E² Memory
Map Register. Their bits are mapped as follows:
SFR Map Register (SFRM) Default = 3F
7
6
0
0
A15-A10
5
A15
4
A14
3
A13
2
A12
1
0
A11 A10
2887 ILL F10
The A15-A10 are upper address bits for the 1K-byte
page where the SFR memory is mapped.
7