X88C75 Datasheet, PDF (4/27 Pages) Xicor Inc. – Port Expander and E2 Memory

X88C75 SLIC^® E²
Page Write Operation
OPERATION
BYTE 0
CE
ALE
A/D0–A/D7
A8–A12
AIN DIN
A12=n
WR
PSEN(RD)
BYTE 1
BYTE 2
LAST BYTE
READ (1)(2)
AFTER tWC READY FOR
NEXT WRITE OPERATION
AIN DIN
A12=n
AIN DIN
A12=n
AIN DIN
A12=n
AIN DOUT
A12=x
AIN
ADDR
AIN
Next Address
tBLC
tWC
2887 ILL F04
Toggle Bit Polling
Because the X88C75 typical write timing is less than the
specified 5ms, Toggle Bit Polling has been provided to
determine the early completion of a write cycle. During
the internal programming cycle, I/O₆ will toggle from “1”
to “0” and “0” to “1” on subsequent attempts to read from
the memory plane that is being updated. When the
internal cycle is complete, the toggling will cease and
the device will be accessible for additional read or write
operations. Due to the dual plane architecture, reads for
polling must occur from the plane that was written; that
is, the state of A₁₂ during a write must match the state
of A₁₂ during polling.
Figure 1. Toggle Bit Polling
OPERATION
LAST BYTE
WRITTEN
CE
I/O6=X
I/O6=X
I/O6=X
I/O6=X
X88C75 READY FOR
NEXT OPERATION
ALE
A/D0–A/D7
A8–A12
AIN DIN
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=n
AIN DOUT
A12=x
AIN
ADDR
WR
RD
2887 ILL F05
4