X88C75 Datasheet, PDF(10/27 Page) Xicor Inc. – Port Expander and E2 Memory

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

X88C75 Datasheet, PDF (10/27 Pages) Xicor Inc. – Port Expander and E2 Memory

◁

X88C75 SLICÂ® E2

Configuration Register (CR)

The Configuration Register is a volatile register used to

configure the operation of the I/O ports. The configura-

tion register allows the microcontroller to designate

whether each of the two ports is an input or output, what

type of output drive is to be used, and what is the polarity

of the two strobe lines, STRA and STRB. The bit map

of configuration register is shown below.

The IRST bit in the configuration register controls the

method used to clear the port interrupt request

flags(INTA, INTB). The interrupts are reset by either

reading the interrupt source or writing to the Interrupt

Status Register. The interrupt must be disabled prior to

changing strobe polarity bits(STPA, SPTB), or port

direction bits (DIRA, DIRB) in CR. Otherwise, any at-

tempt to modify status of these bits may cause an

interrupt to occur.

Port Data Registers (PDR)

The PDRA/PDRB are byte-wide latches which hold port

data. When a port is configured as output, the outputs

of its PDR latch are connected to the port pins. Writing

to PDR generates a pulse on the port strobe pin and

latches the data. If a port is configured as an input, the

inputs of its PDR latch are connected to the port pins.

External data is latched into PDR on the positive edge of

its clock. The port strobe input and strobe polarity bit

(STPA, STPB) are XORed to generate the PDR

input clock.

Figure 11. Configuration Register

Port Pin Registers (PPR)

The read-only Port Pin Registers are used for reading

the current status of the external I/O port pins. Accessing

the PPR causes the values on the port pins to be placed

on the data bus.

The port direction control bits in configuration register

set the direction for the entire port and no control

mechanism is provided to program the direction of

individual pins. However, the ports have a flexible archi-

tecture which allows operating the I/O ports in bidirec-

tional mode using the PPR read feature.

A port can be operated in input/output mode by config-

uring it as an open-drain output port. The port wire-OR

bit (AWO, or BWO in CR) and its port data direction bit

(DIRA, or DIRB in CR) should be set to â1â. The PDR bits

which correspond to the port pins assigned as inputs

should be programmed to â1â. For monitoring the status

of the input pins, the PPR can be read. In this application

the port strobe pin and the PDR latch are in output mode.

In open-drain mode, there are weak internal pull-ups on

the port pins, however external pull-ups must be used for

proper switching of the I/O lines.

STATIC RAM BLOCK

There are 16 bytes of volatile static RAM registers

mapped to the SFR region. They reside in the 200H-

20FH area offset from the SFR base address. Access-

ing these registers has to be done through external RAM

operations for both writes and reads.

IRST 1 AWO BWO DIRA DIRB STPA STPB

Interrupt Request Reset Mode

This bit controls the clearing of the

interrupt request flag.

â0â = Reading the interrupt source

â1â = Writing to the request register

Strobe B â Strobe Pin Polarity

â0â = Active LOW

â1â = Active HIGH

Strobe A â Strobe Pin Polarity

â0â = Active LOW

â1â = Active HIGH

Port A â Outputs

â0â = CMOS

â1â = Open-Drain

Port B â Outputs

â0â = CMOS

â1â = Open-Drain

Port B â Direction Flag

â0â = Input mode

â1â = Output mode

Port A â Direction Flag

â0â = Input mode

â1â = Output mode

2887 ILL F15.1

▷