X5083 Datasheet, PDF (8/21 Pages) Xicor Inc. – CPU Supervisor with 8Kbit SPI EEPROM

X5083
Figure 5. Read Operation Sequence
CS
SCK
SI
0123456789
20 21 22 23 24 25 26 27 28 29 30
Read Instruction
(1 Byte)
Byte Address (2 Byte)
15 14
3210
Data Out
High Impedance
SO
Figure 6. Read Status Operation Sequence
CS
76543210
SCK
01234567
...
Read Status
Instruction
SI
SO
Figure 7. WREN/WRDI Sequence
...
WW
DD
10
B
L
2
B
L
1
B
L
0
SO = Status Reg When no Nonvolatile
Write Cycle
...
CS
SCK
SI
01234567
Instruction
(1 Byte)
High Impedance
SO
REV 1.1.6 6/25/02
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