X5083 Datasheet, PDF (15/21 Pages) Xicor Inc. – CPU Supervisor with 8Kbit SPI EEPROM

X5083
Power-Up and Power-Down Timing
V_CC
V_TRIP
0 Volts
t_R
RESET
t_PURST
t_PURST
V_TRIP
t_F
t_RPD
RESET Output Timing
Symbol
V_TRIP
t_PURST
t_RPD⁽⁵⁾
t_F⁽⁵⁾
t_R⁽⁵⁾
V_RVALID
Parameter
Reset trip point voltage, X5083PT-4.5A (See note 6)
Reset trip point voltage, X5083PT
Reset trip point voltage, X5083PT-2.7A
Reset trip point voltage, X5083PT-2.7
Power-up reset time out
V_CC detect to reset/output
V_CC fall time
V_CC rise time
Reset valid V_CC
Note: (5) This parameter is periodically sampled and not 100% tested.
(6) PT= Package/Temperature
CS vs. RESET Timing
Min.
4.5
4.25
2.85
2.55
100
0.1
0.1
1
Typ.
4.63
4.38
2.93
2.63
200
Max.
4.75
4.5
3.00
2.7
280
500
Unit
V
ms
ns
ns
ns
V
CS
RESET
t_CST
t_WDO
t_RST
t_WDO
t_RST
RESET Output Timing
Symbol
Parameter
t_WDO
t_CST
t_RST
Watchdog time out period,
WD1 = 1, WD0 = 1(default)
WD1 = 1, WD0 = 0
WD1 = 0, WD0 = 1
WD1 = 0, WD0 = 0
CS pulse width to reset the watchdog
Reset time out
Min.
100
450
1
400
100
Typ.
OFF
200
600
1.4
200
Max.
300
800
2
300
Unit
ms
ms
sec
ns
ms
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 15 of 21