X5083 Datasheet, PDF (2/21 Pages) Xicor Inc. – CPU Supervisor with 8Kbit SPI EEPROM

X5083
DESCRIPTION
This device combines four popular functions, Power-on
Reset Control, Watchdog Timer, Supply Voltage Super-
vision, and Block Lock Serial EEPROM Memory in one
package. This combination lowers system cost, reduces
board space requirements, and increases reliability.
Applying power to the device activates the power on
reset circuit which holds RESET active for a period of
time. This allows the power supply and oscillator to sta-
bilize before the processor can execute code.
The Watchdog Timer provides an independent protection
mechanism for microcontrollers. When the microcontroller
PIN CONFIGURATION
8-Lead TSSOP
RESET
V_CC
CS/WDI
SO
1
8
2
3
X5083
7
6
4
5
SCK
SI
V_SS
WP
fails to restart a timer within a selectable time out interval,
the device activates the RESET signal. The user selects
the interval from three preset values. Once selected, the
interval does not change, even after cycling the power.
The device’s low V_CC detection circuitry protects the
user’s system from low voltage conditions, resetting
the system when V_CC falls below the minimum V_CC trip
point. RESET is asserted until V_CC returns to the
proper operating level and stabilizes. Five industry
standard V_TRIP thresholds are available, however, Xicor’s
unique circuits allow the threshold to be reprogrammed to
meet custom requirements or to fine-tune the threshold
for applications requiring higher precision.
8-Lead SOIC, PDIP
CS/WDI
SO
WP
V_SS
1
8
2
7
3 ^X5083 6
4
5
V_CC
RESET
SCK
SI
PIN DESCRIPTION
Pin
(SOIC/ Pin
PDIP) TSSOP Name
Function
1
3 CS/WDI Chip Select Input. CS HIGH, deselects the device and the SO output pin is at a high
impedance state. Unless a nonvolatile write cycle is underway, the device will be in the standby
power mode. CS LOW enables the device, placing it in the active power mode. Prior to the
start of any operation after power up, a HIGH to LOW transition on CS is required.
Watchdog Input. A HIGH to LOW transition on the WDI pin restarts the Watchdog timer. The
absence of a HIGH to LOW transition within the watchdog time out period results in RESET
going active.
2
4
SO Serial Output. SO is a push/pull serial data output pin. A read cycle shifts data out on this pin. The
falling edge of the serial clock (SCK) clocks the data out.
5
7
SI Serial Input. SI is a serial data input pin. Input all opcodes, byte addresses, and memory data
on this pin. The rising edge of the serial clock (SCK) latches the input data. Send all opcodes
(Table 1), addresses and data MSB first.
6
8
SCK Serial Clock. The Serial Clock controls the serial bus timing for data input and output. The rising
edge of SCK latches in the opcode, address, or data bits present on the SI pin. The falling edge of
SCK changes the data output on the SO pin.
3
5
WP Write Protect. When WP is LOW, nonvolatile write operations to the memory are prohibited.
This “Locks” the memory to protect it against inadvertent changes when WP is HIGH, the
device operates normally.
4
6
V_SS Ground
8
2
V_CC Supply Voltage
7
1
RESET Reset Output. RESET is an active LOW, open drain output which goes active whenever V_CC
falls below the minimum V_CC sense level. It will remain active until V_CC rises above the
minimum V_CC sense level for 250ms. RESET goes active if the watchdog timer is enabled and
CS remains either HIGH or LOW longer than the selectable watchdog time out period.
A falling edge of CS will reset the watchdog timer. RESET goes active on power up at about
1V and remains active for 250ms after the power supply stabilizes.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 2 of 21