X5083 Datasheet, PDF (5/21 Pages) Xicor Inc. – CPU Supervisor with 8Kbit SPI EEPROM

X5083
Figure 4. V_TRIP Programming Sequence
New V_CC Applied =
Old V_CC Applied + Error
V_TRIP Programming
Execute
Reset V_TRIP
Sequence
Set V_CC = V_CC Applied =
Desired V_TRIP
Execute
Set V_TRIP
Sequence
Apply 5V to V_CC
Decrement V_CC
(V_CC = V_CC - 50mV)
New V_CC Applied =
Old V_CC Applied - Error
Execute
Reset V_TRIP
Sequence
NO
RESET pin
goes active?
YES
Error ≤ –Emax
Emax = Maximum Desired Error
Measured V_TRIP -
Desired V_TRIP
Error ≥ Emax
–Emax < Error < Emax
DONE
SPI Serial Memory
The memory portion of the device is a CMOS serial
EEPROM array with Xicor’s block lock protection. The
array is internally organized as x 8. The device features
a Serial Peripheral Interface (SPI) and software protocol
allowing operation on a simple four-wire bus.
The device utilizes Xicor’s proprietary Direct Write^™
cell, providing a minimum endurance of 100,000 cycles
and a minimum data retention of 100 years.
The device is designed to interface directly with the
synchronous Serial Peripheral Interface (SPI) of many
popular microcontroller families.
The device monitors the bus and asserts RESET out-
put if the watchdog timer is enabled and there is no bus
activity within the user selectable time out period or the
supply voltage falls below a preset minimum V_TRIP.
The device contains an 8-bit instruction register. It is
accessed via the SI input, with data being clocked in
on the rising edge of SCK. CS must be LOW during the
entire operation.
All instructions (Table 1), addresses and data are
transferred MSB first. Data input on the SI line is
latched on the first rising edge of SCK after CS goes
LOW. Data is output on the SO line by the falling edge
of SCK. SCK is static, allowing the user to stop the
clock and then start it again to resume operations
where left off.
REV 1.1.6 6/25/02
www.xicor.com
Characteristics subject to change without notice. 5 of 21