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X9258 Datasheet, PDF (13/22 Pages) Xicor Inc. – Quad Digital Controlled Potentiometers (XDCP)
X9258
D.C. OPERATING CHARACTERISTICS (Over the recommended operating conditions unless otherwise specified.)
Symbol
ICC1
ICC2
ISB
ILI
ILO
VIH
VIL
VOL
Parameter
VCC supply current (Non-
volatile Write)
VCC supply current (move
wiper, write, read)
VCC current (standby)
Input leakage current
Output leakage current
Input HIGH voltage
Input LOW voltage
Output LOW voltage
Min.
VCC x 0.7
–0.5
Limits
Typ. Max.
1
100
5
10
10
VCC + 0.1
VCC x 0.3
0.4
Unit
mA
µA
µA
µA
µA
V
V
V
Test Conditions
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
fSCL = 400kHz, SDA = Open,
Other Inputs = VSS
SCL = SDA = VCC, Addr. = VSS
VIN = VSS to VCC
VOUT = VSS to VCC
IOL = 3mA
Notes: (1) Absolute linearity is utilized to determine actual wiper voltage versus expected voltage as determined by wiper position when used
as a potentiometer.
(2) Relative linearity is utilized to determine the actual change in voltage between two successive tap positions when used as a potenti-
ometer. It is a measure of the error in step size.
(3) MI = RTOT/255 or (VH/RH—VL/RL)/255, single pot
(4) Max. = all four arrays cascaded together, Typical = individual array resolutions.
ENDURANCE AND DATA RETENTION
Parameter
Minimum endurance
Data retention
Min.
100,000
100
Unit
Data changes per bit per register
years
CAPACITANCE
Symbol
CI/O(5)
CIN(5)
Test
Input/output capacitance (SDA)
Input capacitance (A0, A1, A2, A3, and SCL)
Max.
8
6
Unit
pF
pF
Test Conditions
VI/O = 0V
VIN = 0V
POWER-UP TIMING
Symbol
tPUR(6)
tPUW(6)
tR VCC(7)
Parameter
Power-up to initiation of read operation
Power-up to initiation of write operation
VCC Power up ramp
Min.
0.2
Max.
1
5
50
Unit
ms
ms
V/msec
POWER UP AND DOWN REQUIREMENT
The are no restrictions on the sequencing of the bias supplies VCC, V+, and V- provided that all three supplies
reach their final values within 1msec of each other. At all times, the voltages on the potentiometer pins must be less
than V+ and more than V-. The recall of the wiper position from nonvolatile memory is not in effect until all supplies
reach their final value. The VCC ramp rate spec is always in effect.
Notes: (5) This parameter is periodically sampled and not 100% tested.
(6) tPUR and tPUW are the delays required from the time the third (last) power supply (VCC, V+ or V-) is stable until the specific
instruction can be issued. These parameters are periodically sampled and not 100% tested.
(7) Sample tested only.
REV 1.1.7 2/4/03
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Characteristics subject to change without notice. 13 of 22