WM8946 Datasheet, PDF (99/175 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer

Production Data
WM8946
Figure 39 Multiple Register Write to Specified Address using Auto-increment
Figure 40 Multiple Register Read from Specified Address using Auto-increment
Figure 41 Multiple Register Read from Last Address using Auto-increment
Multiple Write and Multiple Read operations enable the host processor to access sequential blocks of
the data in the WM8946 register map faster than is possible with single register operations. The auto-
increment option is enabled when the AUTO_INC register bit is set. This bit is defined in Table 63.
Auto-increment is disabled by default.
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3-WIRE (SPI) CONTROL MODE
The 3-wire control interface uses the C¯¯S, SCLK and SDA pins.
In 3-wire control mode, a control word consists of 32 bits. The first bit is the read/write bit (R/W),
which is followed by 15 address bits (A14 to A0) that determine which control register is accessed.
The remaining 16 bits (B15 to B0) are data bits, corresponding to the 16 bits in each control register.
In 3-wire mode, every rising edge of SCLK clocks in one data bit from the SDA pin. The data is
latched on the 32^nd falling edge of SCLK after 32 bits of data have been clocked into the device.
In Write operations (R/W=0), all SDA bits are driven by the controlling device.
In Read operations (R/W=1), the SDA pin is driven by the controlling device to clock in the register
address, after which the WM8946 drives the SDA pin to output the applicable data bits.
Similarly to 2-wire control mode, the WM8946 can be set to transmit logic 1 by tri-stating the SDA pin,
rather than pulling it high (SPI_OD = 1). An external pull-up resistor is required to pull the SDA line
high so that the logic 1 can be recognised by the master.
The 3-wire control mode timing is illustrated in Figure 42.
PD, July 2012, Rev 4.3
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