WM8946 Datasheet, PDF (75/175 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer

Production Data
A-law Companding
120
100
80
60
40
20
0
0
0.2
0.4
0.6
0.8
Normalised Input
Figure 30 A-Law Companding
WM8946
1
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
1
The companded data is also inverted as recommended by the G.711 standard (all 8 bits are inverted
for -law, all even data bits are inverted for A-law). Companded data is transmitted in the first 8 MSBs
of its respective data word, and consists of sign (1 bit), exponent (3 bits) and mantissa (4 bits), as
shown in Table 48.
BIT7
BIT[6:4]
BIT[3:0]
SIGN
EXPONENT
MANTISSA
Table 48 8-bit Companded Word Composition
8-bit mode is selected whenever DAC_COMP=1 or ADC_COMP=1. The use of 8-bit data allows
samples to be passed using as few as 8 BCLK cycles per Left/Right Clock frame. When using DSP
mode B, 8-bit data words may be transferred consecutively every 8 BCLK cycles.
8-bit mode (without Companding) may be enabled by setting DAC_COMPMODE=1 or
ADC_COMPMODE=1, when DAC_COMP=0 and ADC_COMP=0.
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PD, July 2012, Rev 4.3
75