WM8946 Datasheet, PDF (139/175 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer

Production Data
WM8946
REGISTER
ADDRESS
R48 (30h)
Right SPK
volume ctrl
BIT
LABEL
DEFAULT
DESCRIPTION
8
SPK_VU
0
Speaker PGA Volume Update
Writing a 1 to this bit will cause the Left and Right
Speaker PGA volumes to be updated simultaneously.
7
SPKR_ZC
0
Right Speaker PGA Zero Cross Detector
0 = Change gain immediately
1 = Change gain on zero cross only
6 SPKR_PGA_M
1
Right Speaker PGA Mute
UTE
0 = Disable Mute
1 = Enable Mute
5:0 SPKR_VOL[5:0 11_1001 Right Speaker PGA Volume
]
00_0000 = -57dB gain
00_0001 = -56dB
…
11_1001 = 0dB
...
11_1111 = +6dB
Register 30h Right SPK volume ctrl
REFER TO
REGISTER BIT
LABEL
DEFAULT
DESCRIPTION
ADDRESS
R49 (31h)
6 BYPL_TO_OU
Line L mixer
TL
control 1
0
Left Input PGA (ADC bypass) to Left Output Mixer
select
0 = Disabled
1 = Enabled
5 MDACL_TO_O
0
Inverted Left DAC to Left Output Mixer select
UTL
0 = Disabled
1 = Enabled
4 MDACR_TO_O
0
Inverted Right DAC to Left Output Mixer select
UTL
0 = Disabled
1 = Enabled
3 DACL_TO_OU
TL
0
Left DAC to Left Output Mixer select
0 = Disabled
1 = Enabled
2 DACR_TO_OU
0
Right DAC to Left Output Mixer select
TL
0 = Disabled
1 = Enabled
1 AUX2_TO_OU
TL
0
AUX2 Audio Input to Left Output Mixer select
0 = Disabled
1 = Enabled
0 AUX1_TO_OU
TL
0
AUX1 Audio Input to Left Output Mixer select
0 = Disabled
1 = Enabled
Register 31h Line L mixer control 1
REFER TO
w
PD, July 2012, Rev 4.3
139