WM8946 Datasheet, PDF (71/175 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer

Production Data
REGISTER
ADDRESS
BIT
LABEL
7
DACR_SRC
6
DACL_SRC
5
BCLK_INV
4
LRCLK_INV
3:2 WL [1:0]
1:0 FMT [1:0]
R21 (15h)
1
DACR_DATINV
DAC Control 1
0
DACL_DATINV
R25 (19h)
1
ADCR_DATINV
ADC Control 1
0
ADCL_DATINV
Table 46 Audio Data Format Control
DEFAULT
WM8946
DESCRIPTION
1
Right DAC Data Source Select
0 = Right DAC outputs left interface
data
1 = Right DAC outputs right
interface data
0
Left DAC Data Source Select
0 = Left DAC outputs left interface
data
1 = Left DAC outputs right interface
data
0
BCLK Invert
0 = BCLK not inverted
1 = BCLK inverted
0
LRCLK Polarity / DSP Mode A-B
select.
Right, left and I²S modes – LRCLK
polarity
0 = Not Inverted
1 = Inverted
DSP Mode – Mode A-B select
0 = MSB is available on 2^nd BCLK
rising edge after LRCLK rising edge
(mode A)
1 = MSB is available on 1^st BCLK
rising edge after LRCLK rising edge
(mode B)
10
Digital Audio Interface Word Length
00 = 16 bits
01 = 20 bits
10 = 24 bits
11 = 32 bits
Note – see “Companding” for the
selection of 8-bit mode.
10
Digital Audio Interface Format
00 = Reserved
01 = Left Justified
10 = I2S format
11 = DSP/PCM mode
0
Right DAC Invert
0 = Right DAC output not inverted
1 = Right DAC output inverted
0
Left DAC Invert
0 = Left DAC output not inverted
1 = Left DAC output inverted
0
Right ADC Invert
0 = Right ADC output not inverted
1 = Right ADC output inverted
0
Left ADC Invert
0 = Left ADC output not inverted
1 = Left ADC output inverted
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PD, July 2012, Rev 4.3
71