WM8946 Datasheet, PDF (102/175 Pages) Wolfson Microelectronics plc – Stereo Low-Power CODEC with Video Buffer

WM8946
REGISTER
ADDRESS
BIT
LABEL
10
SPKL_SPKVDD
_ENA
7
SPKR_OP_ENA
6
SPKL_OP_ENA
3
SPKR_MIX_EN
A
2
SPKL_MIX_ENA
1
DACR_ENA
0
DACL_ENA
Table 65 Power Management Control
DEFAULT
Production Data
DESCRIPTION
0
SPKOUTL enable
0 = Disabled
1 = Enabled
Note that SPKOUTL is also
controlled by SPKL_OP_ENA.
When powering down SPKOUTL,
the SPKL_SPKVDD_ENA bit should
be reset first
0
SPKOUTR enable
0 = Disabled
1 = Enabled
Note that SPKOUTR is also
controlled by
SPKR_SPKVDD_ENA. When
powering up SPKOUTR, the
SPKR_OP_ENA bit should be
enabled first.
0
SPKOUTL enable
0 = Disabled
1 = Enabled
Note that SPKOUTL is also
controlled by SPKL_SPKVDD_ENA.
When powering up SPKOUTL, the
SPKL_OP_ENA bit should be
enabled first
0
Right speaker output mixer enable
0 = Disabled
1 = Enabled
0
Left speaker output mixer enable
0 = Disabled
1 = Enabled
0
Right DAC Enable
0 = Disabled
1 = Enabled
DACR_ENA must be set to 1 when
processing right channel data from
the DAC or Digital Beep Generator.
0
Left DAC Enable
0 = Disabled
1 = Enabled
DACR_ENA must be set to 1 when
processing left channel data from
the DAC or Digital Beep Generator.
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PD, July 2012, Rev 4.3
102