WM8958 Datasheet, PDF (251/377 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

Pre-Production
WM8958
QUICK START-UP AND SHUTDOWN
The default control sequences (see “Control Write Sequencer”) contain only the register writes
necessary to enable or disable specific output drivers. It is therefore necessary to configure the signal
path and gain settings before commanding any of the default start-up sequences.
This section describes minimum control sequences to configure the WM8958 for DAC to Headphone
playback. Note that these sequences are provided for guidance only; application software should be
verified and tailored to ensure optimum performance.
Table 150 describes an example control sequence to enable DAC playback to HPOUT1L and
HPOUT1R path. This involves DAC enable, signal path configuration and mute control, together with
the default “Headphone Cold Start-Up” sequence. Table 151 describes an example control sequence
to disable the direct DAC to Headphone path.
REGISTER
VALUE
DESCRIPTION
R5 (0005h)
0003h
Enable DAC1L and DAC1R
R45 (002Dh)
0100h
Enable path from DAC1L to HPOUT1L
R46 (002Eh)
0100h
Enable path from DAC1R to HPOUT1R
R272 (0110h)
8100h
Initiate Control Write Sequencer at Index Address 0 (00h)
(Headphone Cold Start-Up sequence)
Delay 300ms
Note: Delay must be inserted in the sequence to allow the
Control Write Sequencer to finish. Any control interface writes
to the CODEC will be ignored while the Control Write
Sequencer is running.
R1056 (0420h)
0000h
Soft un-mute DAC1L and DAC1R
Table 150 DAC to Headphone Direct Start-Up Sequence
REGISTER
VALUE
DESCRIPTION
R1056 (0420h)
0200h
Soft mute DAC1L and DAC1R
R272 (0110h)
812Ah
Initiate Control Write Sequencer at Index Address 42 (2Ah)
(Generic Shut-Down)
Delay 525ms
Note: Delay must be inserted in the sequence to allow the
Control Write Sequencer to finish. Any control interface writes
to the CODEC will be ignored while the Control Write
Sequencer is running.
R45 (002Dh)
0000h
Disable path from DAC1L to HPOUT1L
R46 (002Eh)
0000h
Disable path from DAC1R to HPOUT1R
R5 (0005h)
0000h
Disable DAC1L and DAC1R
Table 151 DAC to Headphone Direct Shut-Down Sequence
In both cases, the WSEQ_BUSY bit (in Register R272, see Table 130) will be set to 1 while the
Control Write Sequence runs. When this bit returns to 0, the remaining steps of the sequence may be
executed.
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PP, August 2012, Rev 3.4
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