WM8958 Datasheet, PDF (188/377 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

WM8958
Pre-Production
AIF2 - SIGNAL PATH ENABLE
The AIF2 interface supports two input channels and two output channels. Each of the available
channels can be enabled or disabled using the register bits defined in Table 102. These register
controls are illustrated in Figure 67.
REGISTER
ADDRESS
R4 (0004h)
Power
Management
(4)
BIT
LABEL
13 AIF2ADCL_
ENA
12 AIF2ADCR_
ENA
R5 (0005h)
13 AIF2DACL_
Power
ENA
Management
(5)
12 AIF2DACR_
ENA
R784 (0310h) 1 AIF2TXL_E
AIF2 Control
NA
(1)
0 AIF2TXR_E
NA
Table 102 AIF2 Signal Path Enable
DEFAULT
DESCRIPTION
0
Enable AIF2ADC (Left) output path
0 = Disabled
1 = Enabled
This bit must be set for AIF2 or AIF3 output of
the AIF2ADC (Left) signal.
0
Enable AIF2ADC (Right) output path
0 = Disabled
1 = Enabled
This bit must be set for AIF2 or AIF3 output of
the AIF2ADC (Left) signal.
0
Enable AIF2DAC (Left) input path
0 = Disabled
1 = Enabled
0
Enable AIF2DAC (Right) input path
0 = Disabled
1 = Enabled
1
Enable AIF2DAC (Left) input path
0 = Disabled
1 = Enabled
This bit must be set for AIF2 output of the
AIF2ADC (Left) signal. For AIF3 output only,
this bit can be set to 0.
1
Enable AIF2DAC (Right) input path
0 = Disabled
1 = Enabled
This bit must be set for AIF2 output of the
AIF2ADC (Left) signal. For AIF3 output only,
this bit can be set to 0.
AIF2 - BCLK AND LRCLK CONTROL
The BCLK2 frequency is controlled relative to AIF2CLK by the AIF2_BCLK_DIV divider. See
“Clocking and Sample Rates” for details of the AIF2 clock, AIF2CLK.
The LRCLK2 frequency is controlled relative to BCLK2 by the AIF2DAC_RATE divider.
In Master mode, the LRCLK2 output is generated by the WM8958 when any of the AIF2 channels is
enabled. (Note that, when GPIO6 is configured as ADCLRCLK2, then only the AIF2 DAC channels
will cause LRCLK2 to be output.)
In Slave mode, the LRCLK2 output is disabled by default to allow another digital audio interface to
drive this pin. It is also possible to force the LRCLK2 signal to be output, using the
AIF2DAC_LRCLK_DIR or AIF2ADC_LRCLK_DIR register bits, allowing mixed master and slave
modes. (Note that, when GPIO6 is configured as ADCLRCLK2, then only the AIF2DAC_LRCLK_DIR
bit will force the LRCLK2 signal.)
When the GPIO6 pin is configured as ADCLRCLK2, then the ADCLRCLK2 frequency is controlled
relative to BCLK2 by the AIF2ADC_RATE divider. In this case, the ADCLRCLK2 is dedicated to AIF2
output, and the LRCLK2 pin is dedicated to AIF2 input, allowing different sample rates to be
supported in the two paths.
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In Master mode, with GPIO6 pin configured as ADCLRCLK2, this output is enabled when any of the
AIF2 ADC channels is enabled. The ADCLRCLK2 signal can also be enabled in Slave mode, using
the AIF2ADC_LRCLK_DIR bit, allowing mixed master and slave modes.
PP, August 2012, Rev 3.4
188