WM8958 Datasheet, PDF (209/377 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

Pre-Production
WM8958
REGISTER
ADDRESS
BIT
LABEL
2:0 OPCLK_DIV
R1568
(0620h)
1 ADC_OSR128
Oversampling
0 DAC_OSR128
R1793
(0701h)
Pull Control
(MCLK2)
14 MCLK2_PU
13 MCLK2_PD
R1824
(0720h)
Pull Control
(1)
7 MCLK1_PU
6 MCLK1_PD
Table 119 System Clocking
DEFAULT
000
1
0
0
1
0
0
DESCRIPTION
GPIO Output Clock (OPCLK) Divider
0000 = SYSCLK
0001 = SYSCLK / 2
0010 = SYSCLK / 3
0011 = SYSCLK / 4
0100 = SYSCLK / 5.5
0101 = SYSCLK / 6
0110 = SYSCLK / 8
0111 = SYSCLK / 12
1000 = SYSCLK / 16
1001 to 1111 = Reserved
ADC / Digital Microphone Oversample
Rate Select
0 = Low Power
1 = High Performance
DAC Oversample Rate Select
0 = Low Power
1 = High Performance
MCLK2 Pull-up enable
0 = Disabled
1 = Enabled
MCLK2 Pull-down enable
0 = Disabled
1 = Enabled
MCLK1 Pull-up enable
0 = Disabled
1 = Enabled
MCLK1 Pull-down enable
0 = Disabled
1 = Enabled
BCLK AND LRCLK CONTROL
The digital audio interfaces (AIF1 and AIF2) use BCLK and LRCLK signals for synchronisation. In
master mode, these are output signals, generated by the WM8958. In slave mode, these are input
signals to the WM8958. It is also possible to support mixed master/slave operation.
The BCLK and LRCLK signals are controlled as illustrated in Figure 70. See the “Digital Audio
Interface Control” section for further details of the relevant control registers.
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PP, August 2012, Rev 3.4
209