WM8958 Datasheet, PDF (249/377 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

Pre-Production
WM8958
POWER ON RESET
The WM8958 includes a Power-On Reset (POR) circuit, which is used to reset the digital logic into a
default state after power up. The POR circuit derives its output from AVDD2 and DCVDD. The internal
P¯O¯¯R signal is asserted low when AVDD2 and DCVDD are below minimum thresholds.
The specific behaviour of the circuit will vary, depending on relative timing of the supply voltages.
Typical scenarios are illustrated in Figure 82 and Figure 83.
Figure 82 Power On Reset Timing – AVDD2 enabled/disabled first
Figure 83 Power On Reset Timing - DCVDD enabled/disabled first
The P¯O¯¯R signal is undefined until AVDD2 has exceeded the minimum threshold, V_pora. Once this
threshold has been exceeded, P¯O¯¯R is asserted low and the chip is held in reset. In this condition, all
writes to the control interface are ignored. Once AVDD2 and DCVDD have reached their respective
power on thresholds, P¯O¯¯R is released high, all registers are in their default state, and writes to the
control interface may take place.
Note that a power-on reset period, T_POR, applies after AVDD2 and DCVDD have reached their
respective power on thresholds. This specification is guaranteed by design rather than test.
On power down, P¯O¯¯R is asserted low when either AVDD2 or DCVDD falls below their respective
power-down thresholds.
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PP, August 2012, Rev 3.4
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