WM8958 Datasheet, PDF (224/377 Pages) Wolfson Microelectronics plc – Multi-Channel Audio Hub CODEC for Smartphones

WM8958
Pre-Production
CONTROL INTERFACE
The WM8958 is controlled by writing to registers through a 2-wire serial control interface. Readback is
available for all registers, including Chip ID and power management status.
Note that the Control Interface function can be supported with or without system clocking. Where
possible, the register map access is synchronised with SYSCLK in order to ensure predictable
operation of cross-domain functions. See “Clocking and Sample Rates” for further details of Control
Interface clocking.
The WM8958 is a slave device on the control interface; SCLK is a clock input, while SDAT is a bi-
directional data pin. To allow arbitration of multiple slaves (and/or multiple masters) on the same
interface, the WM8958 transmits logic 1 by tri-stating the SDAT pin, rather than pulling it high. An
external pull-up resistor is required to pull the SDAT line high so that the logic 1 can be recognised by
the master.
In order to allow many devices to share a single 2-wire control bus, every device on the bus has a
unique 8-bit device ID (this is not the same as the address of each register in the WM8958). The
device ID is selectable on the WM8958, using the ADDR pin as shown in Table 127. The LSB of the
Device ID is the Read/Write bit; this bit is set to logic 1 for “Read” and logic 0 for “Write”.
An internal pull-down resistor is enabled by default on the ADDR pin; this can be configured using the
ADDR_PD register bit described in Table 129.
ADDR
DEVICE ID
Low
0011 0100 (34h)
High
0011 0110 (36h)
Table 127 Control Interface Device ID Selection
The WM8958 operates as a slave device only. The controller indicates the start of data transfer with a
high to low transition on SDAT while SCLK remains high. This indicates that a device ID, register
address and data will follow. The WM8958 responds to the start condition and shifts in the next eight
bits on SDAT (8-bit device ID, including Read/Write bit, MSB first). If the device ID received matches
the device ID of the WM8958, then the WM8958 responds by pulling SDAT low on the next clock
pulse (ACK). If the device ID is not recognised or the R/W bit is set incorrectly, the WM8958 returns to
the idle condition and waits for a new start condition and valid address.
If the device ID matches the device ID of the WM8958, the data transfer continues as described
below. The controller indicates the end of data transfer with a low to high transition on SDAT while
SCLK remains high. After receiving a complete address and data sequence the WM8958 returns to
the idle state and waits for another start condition. If a start or stop condition is detected out of
sequence at any point during data transfer (i.e. SDAT changes while SCLK is high), the device
returns to the idle condition.
The WM8958 supports the following read and write operations:
 Single write
 Single read
 Multiple write using auto-increment
 Multiple read using auto-increment
The sequence of signals associated with a single register write operation is illustrated in Figure 73.
Figure 73 Control Interface 2-wire (I2C) Register Write
w
PP, August 2012, Rev 3.4
224